MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 280

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

DMA Controller Module
The DARn should contain the destination (write) address. If the transfer is from a peripheral
device to memory, or from memory to memory, the DARn is loaded with the starting address of
the data block to be written. If the transfer is from memory to a peripheral device, DARn is loaded
with the address of the peripheral data register. This address can be any aligned byte address.
SARn
and
DARn
change
after
each
cycle
depending
on
DCRn[SSIZE,DSIZE,
SINC,DINC,SMOD,DMOD] and on the starting address. Increment values can be 1, 2, 4, or 16
for byte, word, longword, or 16-byte line transfers, respectively. If the address register is
programmed to remain unchanged (no count), the register is not incremented after the data
transfer.
BCRn[BCR] must be loaded with the number of byte transfers to occur. It is decremented by 1, 2,
4, or 16 at the end of each transfer, depending on the transfer size. DSRn[DONE] must be cleared
for channel startup.
As soon as the channel has been initialized, it is started by writing a one to DCRn[START] or
asserting DREQn, depending on the status of DCRn[EEXT]. Programming the channel for
internal requests causes the channel to request the bus and start transferring data immediately. If
the channel is programmed for external request, DREQn must be asserted before the channel
requests the bus.
Changes to DCRn are effective immediately while the channel is active. To avoid problems with
changing a DMA channel setup, write a one to DSRn[DONE] to stop the DMA channel.
14.4.4 Data Transfer
This section describes external requests, auto-alignment, and bandwidth control for DMA
transfers.
14.4.4.1 External Request and Acknowledge Operation
The DMAREQC register in the System Control Module provides a software-controlled
connection matrix between the on- and off-chipplatform DMA request and acknowledge signals.
Writing to this register determines the exact routing of the DMA requests to the four channels of
the DMA module and the acknowledges back to the requesters. If DCRn[EEXT] is set and the
channel is idle, the assertion of the appropriate DREQn or eTPU request activates channel n.
Channels 0, 1, and 2 initiate transfers to an external module by means of DREQ[32:0]. (They are
also available internally to the UART & DTIM interrupt signals.) The request for channel 3 is not
connected externally and is only available internally to the eTPU, UART, and DTIM interrupt
signals. If DCRn[EEXT] = 1 and the channel is idle, the DMA initiates a transfer when DREQn
is asserted or if the eTPU initiates a request.
MCF5271 Reference Manual, Rev. 2
14-16
Freescale Semiconductor