MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 124

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Cache
5-8
30–29
26–25
Bits
31
28
27
24
23
22
Name
CENB
CFRZ
CPDI
CINV
DISD
DISI
—
—
Cache enable. The memory array of the cache is enabled only if CENB is asserted. This
bit, along with the DISI (disable instruction caching) and DISD (disable data caching) bits,
control the cache configuration.
0 Cache disabled
1 Cache enabled
Table 5-5
Reserved, should be cleared.
Disable CPUSHL invalidation. When the privileged CPUSHL instruction is executed, the
cache entry defined by bits [12:4] of the address is invalidated if CPDI = 0. If CPDI = 1, no
operation is performed.
0 Enable invalidation
1 Disable invalidation
Cache freeze. This field allows the user to freeze the contents of the cache. When CFRZ
is asserted line fetches can be initiated and loaded into the line-fill buffer, but a valid cache
entry can not be overwritten. If a given cache location is invalid, the contents of the line-fill
buffer can be written into the memory array while CFRZ is asserted.
0 Normal Operation
1 Freeze valid cache lines
Reserved, should be cleared.
Cache invalidate. The cache invalidate operation is not a function of the CENB state (that
is, this operation is independent of the cache being enabled or disabled). Setting this bit
forces the cache to invalidate all, half, or none of the tag array entries depending on the
state of the DISI, DISD, INVI, and INVD bits. The invalidation process requires several
cycles of overhead plus 512 machine cycles to clear all tag array entries and 64256 cycles
to clear half of the tag array entries, with a single cache entry cleared per machine cycle.
The state of this bit is always read as a zero. After a hardware reset, the cache must be
invalidated before it is enabled.
0 No operation
1 Invalidate all cache locations
Table 5-6
Disable instruction caching. When set, this bit disables instruction caching. This bit, along
with the CENB (cache enable) and DISD (disable data caching) bits, control the cache
configuration. See the CENB definition for a detailed description.
0 Do not disable instruction caching
1 Disable instruction caching
Table 5-5
invalidate all bit.
Disable data caching. When set, this bit disables data caching. This bit, along with the
CENB (cache enable) and DISI (disable instruction caching) bits, control the cache
configuration. See the CENB definition for a detailed description.
0 Do not disable data caching
1 Disable data caching
Table 5-5
invalidate all bit.
Table 5-4. CACR Field Descriptions
describes cache configuration.
describes how to set the cache invalidate all bit.
describes cache configuration and
describes cache configuration and
MCF5271 Reference Manual, Rev. 2
Description
Table 5-6
Table 5-6
describes how to set the cache
describes how to set the cache
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