MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 477

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Figure 25-1
Section 25.5, “Memory Map/Register
25.4
The I
transfer. For I
open collector outputs. The logic AND function is exercised on both lines with external pull-up
resistors.
Out of reset, the I
or responding to a slave transmit address, the I
state. See
Normally, a standard communication is composed of four parts: START signal, slave address
transmission, data transfer, and STOP signal. These are discussed in the following sections.
25.4.1 START Signal
When no other device is bus master (both I2C_SCL and I2C_SDA lines are at logic high), a device
can initiate communication by sending a START signal (see A in
is defined as a high-to-low transition of I2C_SDA while I2C_SCL is high. This signal denotes the
beginning of a data transfer (each data transfer can be several bytes long) and awakens all slaves.
Freescale Semiconductor
• I
• I
• I
• I
• I
I2C_SDA
I2C_SCL
2
C module uses a serial data line (I2C_SDA) and a serial clock line (I2C_SCL) for data
2
2
2
2
2
A
C address register (I2ADR)
C frequency divider register (I2FDR)
C control register (I2CR)
C status register (I2SR)
C data I/O register (I2DR)
Section 25.6.1, “Initialization
I
2
START
Signal
C System Configuration
shows the relationships of the below I
2
C compliance, all devices connected to these two signals must have open drain or
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
msb
1
2
C default state is as a slave receiver. Thus, when not programmed to be a master
2
Figure 25-2. I
Calling Address
3
B
4
5
MCF5271 Reference Manual, Rev. 2
6
2
C Standard Communication Protocol
(Byte complete)
7
Definition":
Interrupt bit set
Sequence,” for exceptions.
R/W ACK
lsb
8
C
Bit
9
2
C module should return to the default slave receiver
D
XXX
I2C_SCL held low while
Interrupt is serviced
msb
D7 D6 D5
1
2
E
C registers, which are described in
2
3
Data Byte
Figure
D4 D3
4
5
25-2). A START signal
D2 D1
6
7
I
2
C System Configuration
lsb
D0
8
ACK
No
Bit
9
STOP
Signal
F
25-3