MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 249

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Chapter 13
Interrupt Controller Modules
13.1
This section details the functionality for the MCF5271 interrupt controller (INTC). The general
features of the MCF5271 interrupt controller block include:
The 34 fully-programmable and seven fixed-level interrupt sources for the interrupt controller on
the MCF5271 handle the complete set of interrupt sources from all of the modules on the device.
This section describes how the interrupt sources are mapped to the interrupt controller logic and
how interrupts are serviced.
13.1.1 68K/ColdFire Interrupt Architecture Overview
Before continuing with the specifics of the MCF5271 interrupt controller, a brief review of the
interrupt architecture of the 68K/ColdFire family is appropriate.
The interrupt architecture of ColdFire is exactly the same as the M68000 family, where there is a
3-bit encoded interrupt priority level sent from the interrupt controller to the core, providing 7
levels of interrupt requests. Level 7 represents the highest priority interrupt level, while level 1 is
the lowest priority. The processor samples for active interrupt requests once per instruction by
comparing the encoded priority level against a 3-bit interrupt mask value (I) contained in bits 10:8
of the machine’s status register (SR). If the priority level is greater than the SR[I] field at the
sample point, the processor suspends normal instruction execution and initiates interrupt exception
processing. Level 7 interrupts are treated as non-maskable and edge-sensitive within the processor,
while levels 1-6 are treated as level-sensitive and may be masked depending on the value of the
SR[I] field. For correct operation, the ColdFire requires that, once asserted, the interrupt source
remain asserted until explicitly disabled by the interrupt service routine.
Freescale Semiconductor
• 41 interrupt sources, organized as:
• Each of the 41 sources has a unique interrupt control register (ICRx) to define the
• Unique vector number for each interrupt source
• Ability to mask any individual interrupt source, plus global mask-all capability
• Supports both hardware and software interrupt acknowledge cycles
• “Wake-up” signal from low-power stop modes
— 34 fully-programmable interrupt sources
— 7 fixed-level interrupt sources
software-assigned levels and priorities within the level
Introduction
MCF5271 Reference Manual, Rev. 2
13-1