MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 355

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

19.2.4.3 Receive Descriptor Active Register (RDAR)
RDAR is a command register, written by the user, that indicates that the receive descriptor ring has
been updated (empty receive buffers have been produced by the driver with the empty bit set).
Whenever the register is written, the RDAR bit is set. This is independent of the data actually
written by the user. When set, the FEC will poll the receive descriptor ring and process receive
frames (provided ECR[ETHER_EN] is also set). Once the FEC polls a receive descriptor whose
empty bit is not set, then the FEC will clear the RDAR bit and cease receive descriptor ring polling
until the user sets the bit again, signifying that additional descriptors have been placed into the
receive descriptor ring.
The RDAR register is cleared at reset and when ECR[ETHER_EN] is cleared.
Freescale Semiconductor
Address
Reset
Reset
31–19
18–0
Bits
W
W
R HB
R
ERR
31
15
0
0
0
See
and
BABR BABT GRA TXF
30
14
0
0
0
Figure 19-3
Table
Name
—
29
13
0
0
0
19-4.
Figure 19-3. Interrupt Mask Register (EIMR)
28
12
0
0
0
Table 19-5. EIMR Field Descriptions
Interrupt mask. Each bit corresponds to an interrupt source defined by the EIR
register. The corresponding EIMR bit determines whether an interrupt condition can
generate an interrupt. At every processor clock, the EIR samples the signal
generated by the interrupting source. The corresponding EIR bit reflects the state of
the interrupt signal even if the corresponding EIMR bit is set.
0 The corresponding interrupt source is masked.
1 The corresponding interrupt source is not masked.
Reserved, should be cleared.
27
11
0
0
0
MCF5271 Reference Manual, Rev. 2
TXB RXF RXB
26
10
0
0
0
25
0
0
0
9
IPSBAR + 0x1008
24
0
0
0
8
MII
23
0
0
7
0
Description
ERR
EB
22
0
0
0
6
LC
21
0
0
0
5
RL
20
0
0
0
4
Memory Map/Register Definition
UN
19
0
0
0
3
18
0
0
0
0
2
17
0
0
0
0
1
16
0
0
0
0
0
19-11