MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 259

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

13.2.1.4 Interrupt Request Level Register (IRLR)
This 7-bit register is updated each machine cycle and represents the current interrupt requests for
each interrupt level, where bit 7 corresponds to level 7, bit 6 to level 6, etc. This register output is
encoded into the 3-bit priority interrupt level driven to the processor core.
13.2.1.5 Interrupt Acknowledge Level and Priority Register (IACKLPR)
Each time an IACK is performed, the interrupt controller responds with the vector number of the
highest priority source within the level being acknowledged. In addition to providing the vector
number directly for the byte-sized IACK read, this 8-bit register is also loaded with information
about the interrupt level and priority being acknowledged. This register provides the association
between the acknowledged “physical” interrupt request number and the programmed interrupt
level/priority. The contents of this read-only register are described in
Freescale Semiconductor
Bits
Bits
7–1
0
7
Name
Name
IRQ
Address
Address
Figure 13-8. IACK Level and Priority Register (IACKLPR)
—
—
Reset
Reset
Figure 13-7. Interrupt Request Level Register (IRLR)
W
W
R
R
Interrupt requests. Represents the prioritized active interrupts for each level.
0 There are no active interrupts at this level
1 There is an active interrupt at this level
Reserved
Reserved
Table 13-11. IACKLPR Field Descriptions
0
0
0
7
7
Table 13-10. IRQLR Field Descriptions
MCF5271 Reference Manual, Rev. 2
0
0
6
6
LEVEL
0
0
5
5
IPSBAR + 0x00_0C18
IPSBAR + 0x00_0C19
IRQ
0
0
4
4
Description
Description
0
0
3
3
2
0
2
0
PRI
Figure 13-8
0
0
1
1
Memory Map/Register Definition
0
0
0
0
0
and
Table
13-11.
13-11