MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 532

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Symmetric Key Hardware Accelerator (SKHA)
The value of data size must be a multiple of 8 for DES/3DES or a multiple of 16 for AES.
However, for CTR mode, data size may be a multiple of 8. If an illegal data size is set, a data size
error will be generated, setting SKESR[DSE] and generating an interrupt request to the interrupt
controller if the DSE bit is not masked.
28.2.1.9 SKHA Input FIFO
The SKHA Input FIFO provides temporary storage for data to be used during processing. The
input to the FIFO is accessible through the address IPSBAR + 0x1B_0020 in the address map. The
input FIFO is a write-only register and attempting to read from this register will always return zero.
If the FIFO is written to when the FIFO level is full then an interrupt will be generated and
SKESR[IFO] bit will be set. The SKSR[IFL] field, described in
Register (SKSR),”
FIFO.
28.2.1.10 SKHA Output FIFO
The SKHA Output FIFO provides temporary storage for data post-processing. The output from
the FIFO is accessible through the address IPSBAR + 0x1B_0024 in the address map. The output
FIFO is a read-only register and attempting to write to this register has no effect. If the output FIFO
is read from when the FIFO level is empty then an interrupt is generated and SKESR[OFU] is set.
The SKSR[OFL] field, described in
polled to monitor how many 32-bit words are currently resident in the FIFO.
28.2.1.11 SKHA Key Data Registers (SKKDRn)
The six 32-bit SKKDRn are write-only and hold the symmetric key. The key should be loaded with
the first four bytes placed in Key 1, followed by Key 2, etc. The key should be loaded before
setting the key size. Any key data beyond the value specified in the SKKSR will be ignored.
28-14
Address
Reset
Reset
W
W
R
R
31
15
0
0
30
14
0
0
can be polled to monitor how many 32-bit words are currently resident in the
Figure 28-14. SKHA Data Size Register (SKDSR)
29
13
0
0
28
12
0
0
MCF5271 Reference Manual, Rev. 2
27
11
0
0
Section 28.2.1.4, “SKHA Status Register (SKSR),”
26
10
0
0
Number of bytes to process
Number of bytes to process
IPSBAR + 0x1B_001C
25
0
0
9
24
0
0
8
23
0
0
7
22
0
6
0
Section 28.2.1.4, “SKHA Status
21
0
0
5
20
0
0
4
19
0
0
3
Freescale Semiconductor
18
0
0
2
17
0
0
1
16
can be
0
0
0