MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 25

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

29.4.3.3
29.4.3.4
29.4.3.5
29.4.3.6
29.4.3.7
29.5
29.5.1
29.5.2
30.1
30.1.1
30.2
30.3
30.3.1
30.4
30.4.1
30.4.2
30.4.3
30.4.4
30.4.5
30.4.6
30.4.7
30.5
30.5.1
30.5.2
30.5.2.1
30.5.2.2
30.5.3
30.5.3.1
30.5.3.2
30.5.3.3
30.6
30.6.1
30.6.1.1
30.6.2
30.7
30.7.1
30.7.2
Freescale Semiconductor
Paragraph
Number
Initialization/Application Information ........................................................................ 29-10
Introduction................................................................................................................... 30-1
External Signal Description .......................................................................................... 30-2
Real-Time Trace Support.............................................................................................. 30-2
Memory Map/Register Definition ................................................................................ 30-5
Background Debug Mode (BDM) .............................................................................. 30-16
Real-Time Debug Support .......................................................................................... 30-37
Processor Status, DDATA Definition......................................................................... 30-40
Restrictions ............................................................................................................. 29-10
Nonscan Chain Operation....................................................................................... 29-11
Overview................................................................................................................... 30-1
Begin Execution of Taken Branch (PST = 0x5) ....................................................... 30-4
Revision A Shared Debug Resources ....................................................................... 30-7
Address Attribute Trigger Register (AATR) ............................................................ 30-7
Address Breakpoint Registers (ABLR, ABHR) ....................................................... 30-8
Configuration/Status Register (CSR)........................................................................ 30-9
Data Breakpoint/Mask Registers (DBR, DBMR)................................................... 30-12
Program Counter Breakpoint/Mask Registers (PBR, PBMR)................................ 30-13
Trigger Definition Register (TDR) ......................................................................... 30-14
CPU Halt................................................................................................................. 30-16
BDM Serial Interface.............................................................................................. 30-17
BDM Command Set................................................................................................ 30-19
Theory of Operation................................................................................................ 30-37
Concurrent BDM and Processor Operation ............................................................ 30-39
User Instruction Set ................................................................................................ 30-40
Supervisor Instruction Set....................................................................................... 30-44
SAMPLE/PRELOAD Instruction......................................................................... 29-9
ENABLE_TEST_CTRL Instruction .................................................................. 29-10
HIGHZ Instruction.............................................................................................. 29-10
CLAMP Instruction ............................................................................................ 29-10
BYPASS Instruction........................................................................................... 29-10
Receive Packet Format ....................................................................................... 30-18
Transmit Packet Format...................................................................................... 30-19
ColdFire BDM Command Format...................................................................... 30-21
Command Sequence Diagrams........................................................................... 30-22
Command Set Descriptions ................................................................................ 30-23
Emulator Mode ................................................................................................... 30-39
MCF5271 Reference Manual, Rev. 2
Debug Support
Contents
Chapter 30
Title
Number
Page
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