MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 141

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MCF5270CAB100

Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets

Specifications of MCF5270CAB100

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
7.2.1
This input is driven by an external clock except when used as a connection to the external crystal
when using the internal oscillator.
7.2.2
This output is an internal oscillator connection to the external crystal.
7.2.3
This output reflects the internal bus clock.
7.2.4
The clock mode is selected during reset and reflected in the PLLMODE, PLLSEL, and PLLREF
bits of the synthesizer status. Once reset is exited, the clock mode cannot be changed.
The clock mode selection during reset configuration is summarized in
7.2.5
The RSTOUT pin is asserted by one of the following:
Freescale Semiconductor
• Internal system reset signal
• FRCRSTOUT bit in the reset control status register (RCR); see
Control Register
EXTAL
XTAL
CLKOUT
CLKMOD[1:0]
RSTOUT
CLKMOD[1:0]
RSTOUT
1
CLKMOD[1]
In 1:1 mode for the MCF5271, f
(RCR).”
0
0
1
1
Name
Table 7-2. Signal Properties (Continued)
Signals
Table 7-3. Clock Mode Selection
CLKMOD[0]
MCF5271 Reference Manual, Rev. 2
Clock mode select inputs
Reset signal from reset controller
0
1
0
1
PLL Bypass Mode (external clock mode)
1:1 Mode
Normal mode with external reference
Normal mode with crystal reference
sys
= 2×f
1
ref_1:1
Function
Clock Mode
Table
Section 10.3.1, “Reset
External Signal Descriptions
7-3.
7-7

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