MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 60

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Signal Descriptions
2.3.6 External Interrupt Signals
Table 2-7
2.3.7 Ethernet Module (FEC) Signals
The following signals are used by the Ethernet module for data and clock signals.
2-10
SDRAM Synchronous
Row Address Strobe
SDRAM Synchronous
Column Address Strobe
SDRAM Write Enable
SDRAM Chip Selects
SDRAM Clock Enable
External Interrupts
Management Data
Management Data
Clock
Transmit Clock
Transmit Enable
Transmit Data 0
Collision
Signal Name
Signal Name
Signal Name
describes the external interrupt signals.
SD_SRAS
SD_SCAS
SD_WE
SD_CS[1:0]
SD_CKE
IRQ[7:1]
EMDIO
EMDC
ETXCLK
ETXEN
ETXD0
ECOL
Abbreviation
Abbreviation
Abbreviation
Table 2-8. Ethernet Module (FEC) Signals
Table 2-6. SDRAM Controller Signals
Table 2-7. External Interrupt Signals
MCF5271 Reference Manual, Rev. 2
Asserted upon detection of a collision and remains asserted while the
SDRAM synchronous row address strobe.
SDRAM synchronous column address strobe.
SDRAM write enable.
SDRAM chip select signals.
SDRAM clock enable.
External interrupt sources. IRQ2 can also be configured as DMA
request signal DREQ2.
Transfers control information between the external PHY and the
media-access controller. Data is synchronous to EMDC. Applies to MII
mode operation. This signal is an input after reset. When the FEC is
operated in 10Mbps 7-wire interface mode, this signal should be
connected to VSS.
In Ethernet mode, EMDC is an output clock which provides a timing
reference to the PHY for data transfers on the EMDIO signal. Applies
to MII mode operation.
Input clock which provides a timing reference for ETXEN, ETXD[3:0]
and ETXER
Indicates when valid nibbles are present on the MII. This signal is
asserted with the first nibble of a preamble and is negated before the
first ETXCLK following the final nibble of the frame.
ETXD0 is the serial output Ethernet data and is only valid during the
assertion of ETXEN. This signal is used for 10-Mbps Ethernet data. It
is also used for MII mode data in conjunction with ETXD[3:1].
collision persists. This signal is not defined for full-duplex mode.
Function
Function
Function
Freescale Semiconductor
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
I
I
I