MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 567

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

The assertion of BKPT should be considered in the following two special cases:
The CSR[27–24] bits indicate the halt source, showing the highest priority source for multiple halt
conditions.
30.5.2 BDM Serial Interface
When the CPU is halted and PST reflects the halt status, the development system can send
unrestricted commands to the debug module. The debug module implements a synchronous
protocol using two inputs (DSCLK and DSI) and one output (DSO), where DSO is specified as a
delay relative to the rising edge of the processor clock. See
serves as the serial communication channel master and must generate DSCLK.
The serial channel operates at a frequency from DC to 1/5 of the PSTCLK frequency. The channel
uses full-duplex mode, where data is sent and received simultaneously by both master and slave
devices. The transmission consists of 17-bit packets composed of a status/control bit and a 16-bit
data word. As shown in
when DSCLK is high; that is, DSI is sampled and DSO is driven.
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4. The assertion of the BKPT input is treated as a pseudo-interrupt; that is, the halt condition
• After the system reset signal is negated, the processor waits for 16 processor clock cycles
• The ColdFire architecture also handles a special case of BKPT being asserted while the
is postponed until the processor core samples for halts/interrupts. The processor samples
for these conditions once during the execution of each instruction. If there is a pending
halt condition at the sample time, the processor suspends execution and enters the halted
state.
before beginning reset exception processing. If the BKPT input is asserted within eight
cycles after RESET is negated, the processor enters the halt state, signaling halt status (0xF)
on the PST outputs. While the processor is in this state, all resources accessible through the
debug module can be referenced. This is the only chance to force the processor into
emulation mode through CSR[EMU].
After system initialization, the processor’s response to the
of BDM commands performed while it is halted for a breakpoint. Specifically, if the PC
register was loaded, the
control to the instruction address in the PC, bypassing normal reset exception processing.
If the PC was not loaded, the
continue reset exception processing.
processor is stopped by execution of the STOP instruction. For this case, the processor exits
the stopped mode and enters the halted state, at which point, all BDM commands may be
exercised. When restarted, the processor continues by executing the next sequential
instruction, that is, the instruction following the STOP opcode.
Figure
30-12, all state transitions are enabled on a rising edge of PSTCLK
GO
MCF5271 Reference Manual, Rev. 2
command causes the processor to exit halted state and pass
GO
command causes the processor to exit halted state and
Table
GO
30-1. The development system
command depends on the set
Background Debug Mode (BDM)
30-17