MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 122

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Cache
line-fill buffer versus its corresponding cache location. At the time of the miss, the hardware
indicator is set, marking the line-fill buffer as “most recently used.” If a subsequent access occurs
to the cache location defined by bits [12:4] (or bits [11:4] for split configurations of the fill buffer
address), the data in the cache memory array is now most recently used, so the hardware indicator
is cleared. In all cases, the indicator defines whether the contents of the line-fill buffer or the
memory data array are most recently used. At the time of the next cache miss, the contents of the
line-fill buffer are written into the memory array if the entire line is present, and the line-fill buffer
data is still most recently used compared to the memory array.
Generally, longword references are used for sequential instruction fetches. If the processor
branches to an odd word address, a word-sized instruction fetch is generated.
For instruction fetches, the fill buffer can also be used as temporary storage for line-sized bursts
of non-cacheable references under control of CACR[CEIB]. With this bit set, a noncacheable
instruction fetch is processed as defined by
loaded and subsequent references can hit in the buffer, but the data is never loaded into the memory
array.
Table 5-2
fetch.
5.2
Three supervisor registers define the operation of the cache and local bus controller: the cache
control register (CACR) and two access control registers (ACR0, ACR1).
the memory map of the cache and access control registers.
The following lists several keynotes regarding the programming model table:
5-6
• The CACR and ACRs can only be accessed in supervisor mode using the MOVEC
instruction with an Rc value of 0x002, 0x004 and 0x005, respectively.
shows the relationship between CACR bits CENB and CEIB and the type of instruction
Memory Map/Register Definition
[CENB]
CACR
0
0
1
1
1
Table 5-2. Instruction Cache Operation as Defined by CACR
[CEIB]
CACR
X
0
1
0
1
Instruction Fetch
Noncacheable
Noncacheable
Cacheable
Type of
N/A
N/A
MCF5271 Reference Manual, Rev. 2
Cache is completely disabled; all instruction fetches
are word or longword in size.
All instruction fetches are word or longword in size
Fetch size is defined by
line-fill buffer can be written into the memory array
All instruction fetches are word or longword in size,
and not loaded into the line-fill buffer
Instruction fetch size is defined by
loaded into the line-fill buffer, but are never written
into the memory array.
Table
5-2. For this condition, the line-fill buffer is
Description
Table 5-1
and contents of the
Table 5-1
Table 5-3
Freescale Semiconductor
and
below shows