MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 253

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

The registers and their locations are defined in
address for each interrupt controller. The base addresses for the interrupt controllers are listed
below:
Freescale Semiconductor
1
0xC1C - 0xC3C &
This address space only contains the SWIACK and L1ACK-L7IACK registers. See
“Software and Level n IACK Registers (SWIACKR,
IPSBAR Offset
0xC0C
0xC4C
0xC5C
0xC6C
0xC00
0xC04
0xC08
0xC10
0xC14
0xC18
0xC40
0xC44
0xC48
0xC50
0xC54
0xC58
0xC60
0xC64
0xC68
0xC70
0xC74
0xC78
Global IACK Registers Space
Interrupt Controller Number
Table 13-2. Interrupt Controller Base Addresses
Table 13-3. Interrupt Controller Memory Map
INTC0
Bits[31:24]
Reserved
IRLR[7:1]
ICR04
ICR08
ICR12
ICR16
ICR20
ICR24
ICR28
ICR32
ICR36
ICR40
ICR44
ICR48
ICR52
ICR56
MCF5271 Reference Manual, Rev. 2
Interrupt Force Register High (INTFRCH), [63:32]
1
Interrupt Pending Register High (IPRH), [63:32]
Interrupt Force Register Low (INTFRCL), [31:1]
Interrupt Pending Register Low (IPRL), [31:1]
Interrupt Mask Register High (IMRH), [63:32]
Interrupt Mask Register Low (IMRL), [31:0]
IACKLPR[7:0]
Bits[23:16]
ICR01
ICR05
ICR09
ICR13
ICR17
ICR21
ICR25
ICR29
ICR33
ICR37
ICR41
ICR45
ICR49
ICR53
ICR57
Table
L1IACK–L7IACK)" for more information
Reserved
13-3. The offsets listed start from the base
Bits[15:8]
IPSBAR + 0xC00
IPSBAR + 0xF00
ICR02
ICR06
ICR10
ICR14
ICR18
ICR22
ICR26
ICR30
ICR34
ICR38
ICR42
ICR46
ICR50
ICR54
ICR58
Base Address
Reserved
Section 13.2.1.7,
Memory Map/Register Definition
Bits[7:0]
ICR03
ICR07
ICR11
ICR15
ICR19
ICR23
ICR27
ICR31
ICR35
ICR39
ICR43
ICR47
ICR51
ICR55
ICR59
13-5