MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 573

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

30.5.3.3 Command Set Descriptions
The following sections describe the commands summarized in
Freescale reserves unassigned command opcodes for future expansion. Unused command formats
in any revision level perform a
30.5.3.3.1 Read A/D Register (
Read the selected address or data register and return the 32-bit result. A bus error response is
returned if the CPU core is not halted.
Command/Result Formats:
Command Sequence:
Freescale Semiconductor
• In cycle 3, the development system supplies the low-order 16 address bits. The debug
• At the completion of cycle 3, the debug module initiates a memory read operation. Any
• Results are returned in the two serial transfer cycles after the memory access completes. For
Command
Result
module always returns a not-ready response.
serial transfers that begin during a memory access return a not-ready response.
any command performing a byte-sized memory read operation, the upper 8 bits of the
response data are undefined and the referenced data is returned in the lower 8 bits. The next
command’s opcode is sent to the debug module during the final transfer. If a memory or
register access is terminated with a bus error, the error status (S = 1, DATA = 0x0001) is
returned instead of result data.
A
memory-referencing cycle. Otherwise, the debug module can accept a
new serial transfer after 32 processor clock periods.
The BDM status bit (S) is 0 for normally completed commands; S = 1
for illegal commands, not-ready responses, and transfers with
bus-errors.
receive packet format.
15
not-ready
14
0x2
Figure 30-17.
13
Section 30.5.2, “BDM Serial
12
response
NOP
MCF5271 Reference Manual, Rev. 2
11
and return an illegal command response.
RAREG
RAREG
10
can
0x1
/
RDREG
NOTE
NOTE
/
9
RDREG
be
D[31:16]
8
D[15:0]
)
ignored
Command Format
7
Interface,” describes the
6
0x8
Table
except
5
30-18.
4
during
Background Debug Mode (BDM)
A/D
3
2
a
Register
1
0
30-23