MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 482

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

I
25.4.8 Handshaking and Clock Stretching
The clock synchronization mechanism can be used as a handshake in data transfers. Slave devices
can hold I2C_SCL low after completing one byte transfer. In such a case, the clock mechanism
halts the bus clock and forces the master clock into wait states until the slave releases I2C_SCL.
Slaves may also slow down the transfer bit rate. After the master has driven I2C_SCL low, the
slave can drive I2C_SCL low for the required period and then release it. If the slave I2C_SCL low
period is longer than the master I2C_SCL low period, the resulting I2C_SCL bus signal low period
is stretched.
25.5
Table 25-1
25.5.1 I
The I2ADR holds the address the I
address sent on the bus during the address transfer.
25-8
2
C Interface
Bits
7–1
0
IPSBAR Offset
Memory Map/Register Definition
0x030C
2
lists the configuration registers used in the I
0x0300
0x0304
0x0308
0x0310
C Address Register (I2ADR)
Name
ADR
Address
—
Reset
W
R
Mnemonic
Slave address. Contains the specific slave address to be used by the I
mode is the default I
Reserved, should be cleared.
I2ADR
I2FDR
Figure 25-9. I
I2CR
I2DR
I2SR
0
7
Table 25-1. I
Table 25-2. I2ADR Field Descriptions
MCF5271 Reference Manual, Rev. 2
0
2
6
C responds to when addressed as a slave. Note that it is not the
2
I
2
2
C Address Register (I2ADR)
0
C mode for an address match on the bus.
5
2
C Frequency Divider Register
C Interface Memory Map
IPSBAR + 0x00_0300
I
I
I
2
2
I
2
C Data I/O Register
C Address Register
2
C Control Register
C Status Register
ADR
0
4
[31:24]
Description
2
0
3
C interface.
2
0
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
[23:0]
0
0
0
Freescale Semiconductor
2
C module. Slave
Access
R/W
R/W
R/W
R/W
R/W