MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 247

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

12.4
12.4.1 Overview
Initial pin function is determined during reset configuration. The pin assignment registers allow
the user to select among various primary functions and general purpose I/O after reset.
Most pins are configured as general purpose I/O by default. The notable exceptions to this are
external bus control pins, address/data pins, and chip select pins. These pins are configured for
their primary functions after reset.
Every general purpose I/O pin is individually configurable as an input or an output via a data
direction register (PDDR_x).
Every GPIO port has an output data register (PODR_x) and a pin data register (PPDSDR_x) to
monitor and control the state of its pins. Data written to a PODR_x register is stored and then
driven to the corresponding port x pins configured as outputs.
Reading a PODR_x register returns the current state of the register regardless of the state of the
corresponding pins.
Reading a PPDSDR_x register returns the current state of the corresponding pins when configured
as general purpose I/O, regardless of whether the pins are inputs or outputs.
Every GPIO port has a PPDSDR_x register and a clear register (PCLRR_x) for setting or clearing
individual bits in the PODR_x register.
Freescale Semiconductor
Bits
7–1
0
Functional Description
Figure 12-43. Timer Drive Strength Control Register (DSCR_TIMER)
DSCR_
TIMER
Name
Address
—
Reset
W
R
Table 12-22. DSCR_TIMER Field Descriptions
Note: Reset state is 0 when RCON = 1 and is the value of D[21] when
RCON = 0
Reserved, should be cleared.
Timer drive strength. This bit sets the drive strength on the DT3IN, DT3OUT, DT2IN,
DT2OUT, DT1IN, DT1OUT, DT0IN, and DT0OUT pins.
0 Pins set at low drive
1 Pins set at high drive
0
0
7
0
0
6
MCF5271 Reference Manual, Rev. 2
0
0
5
IPSBAR + 0x10_0055
0
0
4
Description
0
0
3
2
0
0
1
0
0
See Note
DSCR_
TIMER
0
Functional Description
12-31