MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 174

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Power Management
8.3.2.16 Clock Module
In wait and doze modes, the clocks to the CPU and SRAM will be stopped and the system clocks
to the peripherals are enabled. Each module may disable the module clocks locally at the module
level. In stop mode, all clocks to the system will be stopped.
During stop mode, the PLL continues to run. The external CLKOUT signal may be enabled or
disabled when the device enters stop mode, depending on the LPCR[STPMD] bit settings.
The external CLKOUT output pin may be disabled to lower power consumption via the
SYNCR[DISCLK] bit. The external CLKOUT pin function is enabled by default at reset.
8.3.2.17 Edge Port
In wait and doze modes, the edge port continues to operate normally and may be configured to
generate interrupts (either an edge transition or low level on an external pin) to exit the low-power
modes.
In stop mode, there is no system clock available to perform the edge detect function. Thus, only
the level detect logic is active (if configured) to allow any low level on the external interrupt pin
to generate an interrupt (if enabled) to exit the stop mode.
8.3.2.18 Watchdog Timer
In stop mode (or in wait/doze mode, if so programmed), the watchdog ceases operation and freezes
at the current value. When exiting these modes, the watchdog resumes operation from the stopped
value. It is the responsibility of software to avoid erroneous operation.
When not stopped, the watchdog may generate a reset to exit the low-power modes.
8.3.2.19 Programmable Interrupt Timers (PIT0, PIT1, PIT2 and PIT3)
In stop mode (or in doze mode, if so programmed), the programmable interrupt timer (PIT) ceases
operation, and freezes at the current value. When exiting these modes, the PIT resumes operation
from the stopped value. It is the responsibility of software to avoid erroneous operation.
When not stopped, the PIT may generate an interrupt to exit the low-power modes.
8.3.2.20 BDM
Entering halt mode via the BDM port (by asserting the external BKPT pin) will cause the CPU to
exit any low-power mode.
MCF5271 Reference Manual, Rev. 2
8-10
Freescale Semiconductor