MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 433

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

The command and data RAM in the QSPI are indirectly accessible with QDR and QAR as 48
separate locations that comprise 16 words of transmit data, 16 words of receive data, and 16 bytes
of commands.
Freescale Semiconductor
Address
Reset
BIts
7–4
15
14
13
12
11
10
W
R WCE
9
8
3
2
1
0
FB
15
0
ABR
WCEFB
WCEFE
ABRTB
ABRTL
ABRTE
TB
WCEF
SPIFE
Name
14
ABRT
0
SPIF
—
—
—
—
13
0
0
Write collision access error enable. A write collision occurs during a data transfer when the
RAM entry containing the command currently being executed is written to by the CPU with
the QDR. When this bit is asserted, the write access to QDR results in an access error.
Abort access error enable. An abort occurs when QDLYR[SPE] is cleared during a transfer.
When set, an attempt to clear QDLYR[SPE] during a transfer results in an access error.
Reserved, should be cleared.
Abort lock-out. When set, QDLYR[SPE] cannot be cleared by writing to the QDLYR.
QDLYR[SPE] is only cleared by the QSPI when a transfer completes.
Write collision interrupt enable. Interrupt enable for WCEF. Setting this bit enables the
interrupt, and clearing it disables the interrupt.
Abort interrupt enable. Interrupt enable for ABRT flag. Setting this bit enables the interrupt,
and clearing it disables the interrupt.
Reserved, should be cleared.
QSPI finished interrupt enable. Interrupt enable for SPIF. Setting this bit enables the
interrupt, and clearing it disables the interrupt.
Reserved, should be cleared.
Write collision error flag. Indicates that an attempt has been made to write to the RAM entry
that is currently being executed. Writing a 1 to this bit clears it and writing 0 has no effect.
Abort flag. Indicates that QDLYR[SPE] has been cleared by the user writing to the QDLYR
rather than by completion of the command queue by the QSPI. Writing a 1 to this bit clears
it and writing 0 has no effect.
Reserved, should be cleared.
QSPI finished flag. Asserted when the QSPI has completed all the commands in the
queue. Set on completion of the command pointed to by QWR[ENDQP], and on
completion of the current command after assertion of QWR[HALT]. In wraparound mode,
this bit is set every time the command pointed to by QWR[ENDQP] is completed. Writing
a 1 to this bit clears it and writing 0 has no effect.
Figure 23-7. QSPI Interrupt Register (QIR)
ABR
TL
12
0
Table 23-7. QIR Field Descriptions
WCE
FE
11
0
MCF5271 Reference Manual, Rev. 2
ABR
TE
10
0
0
0
9
IPSBAR + 0x00_034C
SPIFE
0
8
0
0
7
Description
0
0
6
0
0
5
0
0
4
WCEF ABRT
Memory Map/Register Definition
0
3
0
2
0
0
1
SPIF
0
0
23-13