MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 324

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Synchronous DRAM Controller Module
18.3.2 DRAM Address and Control Registers (DACR0/DACR1)
The DACRn registers, shown in
control bits for memory blocks 0 and 1 of the SDRAM controller. Address and timing are also
controlled by bits in DACRn.
18-6
10–9
Bits
8–0
12
11
Name
RTIM
COC
RC
IS
Table 18-4. DCR Field Descriptions (Continued)
Command on SDRAM clock enable (SD_CKE). Implementations that use external
multiplexing (NAM = 1) must support command information to be multiplexed onto the
SDRAM address bus.
0 SD_CKE functions as a clock enable; self-refresh is initiated by the SDRAM controller
1 SD_CKE drives command information. Because SD_CKE is not a clock enable,
Initiate self-refresh command.
0 Take no action or issue a
1 If DCR[COC] = 0, the SDRAM controller sends a
Refresh timing. Determines the timing operation of auto-refresh in the SDRAM controller.
Specifically, it determines the number of bus clocks inserted between a
the next possible
controlled by the SDRAM controller. This corresponds to t
00 3 clocks
01 6 clocks
1x 9 clocks
Refresh count. Controls refresh frequency. The number of bus clocks between refresh
cycles is (RC + 1) x 16. Refresh can range from 16–8192 bus clocks to accommodate both
standard and low-power SDRAMs with bus clock operation from less than 2 MHz to greater
than 50 MHz.
The following example calculates RC for an auto-refresh period for 4096 rows to receive
64 ms of refresh every 15.625 µs for each row (1172 bus clocks at 75 MHz). This operation
is the same as in asynchronous mode.
# of bus clocks = 1172 = (RC field + 1) x 16
RC = (1172 bus clocks/16) -1 = 72.25, which rounds to 72; therefore, RC = 0x48.
through DCR[IS].
self-refresh cannot be used (setting DCR[IS]). Thus, external logic must be used if this
functionality is desired. External multiplexing is also responsible for putting the
command information on the proper address bit.
to put them in low-power, self-refresh state where they remain until IS is cleared. When
IS is cleared, the controller sends a
The refresh counter is suspended while the SDRAMs are in self-refresh; the SDRAM
controls the refresh period.
MCF5271 Reference Manual, Rev. 2
Figure
ACTV
18-3, contain the base address compare value and the
command. This same timing is used for both memory blocks
SELFX
command to exit self refresh.
SELFX
Description
command for the SDRAMs to exit self-refresh.
SELF
command to both SDRAM blocks
RC
in the SDRAM specifications.
Freescale Semiconductor
REF
command and