MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 79

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

3.7
3.7.1
The exact processor response to an access error depends on the type of memory reference being
performed. For an instruction fetch, the processor postpones the error reporting until the faulted
reference is needed by an instruction for execution. Therefore, faults that occur during instruction
prefetches that are then followed by a change of instruction flow do not generate an exception.
When the processor attempts to execute an instruction with a faulted opword and/or extension
words, the access error is signaled and the instruction aborted. For this type of exception, the
programming model has not been altered by the instruction generating the access error.
If the access error occurs on an operand read, the processor immediately aborts the current
instruction’s execution and initiates exception processing. In this situation, any address register
updates attributable to the auto-addressing modes, (for example, (An)+,-(An)), have already been
performed, so the programming model contains the updated An value. In addition, if an access
error occurs during the execution of a MOVEM instruction loading from memory, any registers
already updated before the fault occurs contain the operands from memory.
The V2 ColdFire processor uses an imprecise reporting mechanism for access errors on operand
writes. Because the actual write cycle may be decoupled from the processor’s issuing of the
operation, the signaling of an access error appears to be decoupled from the instruction that
generated the write. Accordingly, the PC contained in the exception stack frame merely represents
the location in the program when the access error was signaled. All programming model updates
associated with the write instruction are completed. The NOP instruction can collect access errors
for writes. This instruction delays its execution until all previous operations, including all pending
write operations, are complete. If any previous write terminates with an access error, it is
guaranteed to be reported on the NOP instruction.
3.7.2
Any attempted execution transferring control to an odd instruction address (that is, if bit 0 of the
target address is set) results in an address error exception.
Any attempted use of a word-sized index register (Xn.w) or a scale factor of 8 on an indexed
effective addressing mode generates an address error as does an attempted execution of a
full-format indexed addressing mode.
3.7.3
Any attempted execution of an illegal 16-bit opcode (except for line-A and line-F opcodes)
generates an illegal instruction exception (vector 4). Additionally, any attempted execution of any
non-MAC line-A and most line-F opcode generates their unique exception types, vector numbers
Freescale Semiconductor
Processor Exceptions
Access Error Exception
Address Error Exception
Illegal Instruction Exception
MCF5271 Reference Manual, Rev. 2
Processor Exceptions
3-13