MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 262

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Interrupt Controller Modules
13.2.1.7 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)
The eight IACK registers can be explicitly addressed via the CPU, or implicitly addressed via a
processor-generated interrupt acknowledge cycle during exception processing. In either case, the
interrupt controller’s actions are very similar.
First, consider an IACK cycle to a specific level: that is, a level-n IACK. When this type of IACK
arrives in the interrupt controller, the controller examines all the currently-active level n interrupt
requests, determines the highest priority within the level, and then responds with the unique vector
number corresponding to that specific interrupt source. The vector number is supplied as the data
for the byte-sized IACK read cycle. In addition to providing the vector number, the interrupt
13-14
Sourc
43–63
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
e
Modul
MDHA
SKHA
RNG
PIT0
PIT1
PIT2
PIT3
FEC
e
Table 13-13. Interrupt Source Assignment For INTC (Continued)
X_INTB
R_INTF
R_INTB
HBERR
X_INTF
EBERR
BABR
BABT
GRA
Flag
INT
PIF
PIF
PIF
PIF
UN
MII
RL
LC
MI
EI
Transmit frame interrupt
Transmit buffer interrupt
Transmit FIFO underrun
Collision retry limit
Receive frame interrupt
Receive buffer interrupt
MII interrupt
Late collision
Heartbeat error
Graceful stop complete
Ethernet bus error
Babbling transmit error
Babbling receive error
PIT interrupt flag
PIT interrupt flag
PIT interrupt flag
PIT interrupt flag
RNG interrupt flag
SKHA interrupt flag
MDHA interrupt flag
Source Description
MCF5271 Reference Manual, Rev. 2
Not used
Write X_INTF = 1
Write X_INTB = 1
Write UN = 1
Write RL = 1
Write R_INTF = 1
Write R_INTB = 1
Write MII = 1
Write LC = 1
Write HBERR = 1
Write GRA = 1
Write EBERR = 1
Write BABT = 1
Write BABR = 1
Write PIF = 1 or write PMR
Write PIF = 1 or write PMR
Write PIF = 1 or write PMR
Write PIF = 1 or write PMR
Write RNGCR[CI] = 1
Write SKCMR[CI] = 1
Write MDCMR[CI] = 1
Flag Clearing Mechanism
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