MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 61

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

2.3.8 I
Table 2-9
2.3.9 Queued Serial Peripheral Interface (QSPI)
Table 2-10
Freescale Semiconductor
Receive Clock
Receive Data Valid
Receive Data 0
Carrier Receive Sense ECRS
Transmit Data 1–3
Transmit Error
Receive Data 1–3
Receive Error
Serial Clock
Serial Data
Signal Name
Signal Name
2
describes the I
C I/O Signals
describes QSPI signals.
Table 2-8. Ethernet Module (FEC) Signals (Continued)
ERXCLK
ERXDV
ERXD0
ETXD[3:1]
ETXER
ERXD[3:1]
ERXER
I2C_SCL
I2C_SDA
Abbreviation
Abbreviation
2
C serial interface module signals.
MCF5271 Reference Manual, Rev. 2
Provides a timing reference for ERXDV, ERXD[3:0], and ERXER.
Asserting the receive data valid (ERXDV) input indicates that the PHY
has valid nibbles present on the MII. ERXDV should remain asserted
from the first recovered nibble of the frame through to the last nibble.
Assertion of ERXDV must start no later than the SFD and exclude any
EOF.
ERXD0 is the Ethernet input data transferred from the PHY to the
media-access controller when ERxDV is asserted. This signal is used
for 10-Mbps Ethernet data. This signal is also used for MII mode
Ethernet data in conjunction with ERXD[3:1].
When asserted, indicates that transmit or receive medium is not idle.
Applies to MII mode operation.
In Ethernet mode, these pins contain the serial output Ethernet data
and are valid only during assertion of ETXEN in MII mode.
In Ethernet mode, when ETXER is asserted for one or more clock
cycles while ETXEN is also asserted, the PHY sends one or more
illegal symbols. ETXER has no effect at 10 Mbps or when ETXEN is
negated. Applies to MII mode operation.
In Ethernet mode, these pins contain the Ethernet input data
transferred from the PHY to the Media Access Controller when
ERXDV is asserted in MII mode operation.
In Ethernet mode, ERXER—when asserted with ERXDV—indicates
that the PHY has detected an error in the current frame. When
ERXDV is not asserted ERXER has no effect. Applies to MII mode
operation.
Open-drain clock signal for the for the I
by the I
the clock input when the I
Open-drain signal that serves as the data input/output for the I
interface.
Table 2-9. I
2
C module when the bus is in the master mode or it becomes
2
C I/O Signals
2
C is in the slave mode.
Function
Function
2
C interface. Either it is driven
Signal Primary Functions
2
C
I/O
I/O
I/O
I/O
O
O
I
I
I
I
I
I
2-11