MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 572

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Debug Support
Operands and addresses are transferred most-significant word first. In the following descriptions
of the BDM command set, the optional set of extension words is defined as address, data, or
operand data.
30.5.3.2 Command Sequence Diagrams
The command sequence diagram in
bubble represents a 17-bit bus transfer. The top half of each bubble indicates the data the
development system sends to the debug module; the bottom half indicates the debug module’s
response to the previous development system commands. Command and result transactions
overlap to minimize latency.
The sequence is as follows:
30-22
• In cycle 1, the development system command is issued (
• In cycle 2, the development system supplies the high-order 16 address bits. The debug
READ (LONG)
Commands transmitted to the debug module
Responses from the debug module
module responds with either the low-order results of the previous command or a command
complete status of the previous command, if no results are required.
module returns a not-ready response unless the received command is decoded as
unimplemented, which is indicated by the illegal command encoding. If this occurs, the
development system should retransmit the command.
???
Command code transmitted during this cycle
Results from previous command
’NOT READY’
MS ADDR
’ILLEGAL’
Sequence taken if illegal command
is received by debug module
Figure 30-16. Command Sequence Diagram
XXX
High-order 16 bits of memory address
MCF5271 Reference Manual, Rev. 2
Figure 30-16
’NOT READY’
’NOT READY’
Data used from this transfer
NEXT CMD
LS ADDR
Low-order 16 bits of memory address
Non-serial-related
shows serial bus traffic for commands. Each
LOCATION
MEMORY
activity
READ
READ
’NOT READY’
MS RESULT
Sequence taken if bus error
occurs on memory access
Sequence taken if operation
has not completed
High- and low-order 16 bits of result
in this example). The debug
BERR
XXX
XXX
XXX
Freescale Semiconductor
’NOT READY’
LS RESULT
NEXT CMD
NEXT CMD
Command
Code
Next