MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 199

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Chapter 11
System Control Module (SCM)
11.1 Introduction
This section details the functionality of the System Control Module (SCM) which provides the
programming model for the System Access Control Unit (SACU), the system bus arbiter, a 32-bit
core watchdog timer (CWT), and the system control registers and logic. Specifically, the system
control includes the internal peripheral system (IPS) base address register (IPSBAR), the
processor’s dual-port RAM base address register (RAMBAR), and system control registers that
include the core watchdog timer control.
11.1.1 Overview
The SCM provides the control and status for a variety of functions including base addressing and
address space masking for both the IPS peripherals and resources (IPSBAR) and the ColdFire core
memory space (RAMBAR). The MCF5271 CPU core supports one memory bank for the internal
SRAM.
The SACU provides the mechanism needed to implement secure bus transactions to the system
address space.
The programming model for the system bus arbitration resides in the SCM. The SCM sources the
necessary control signals to the arbiter for bus master management.
The CWT provides a means of preventing system lockup due to uncontrolled software loops via a
special software service sequence. If periodic software servicing action does not occur, the CWT
times out with a programmed response (interrupt) to allow recovery or corrective action to be
taken.
11.1.2 Features
The SCM includes these distinctive features:
Freescale Semiconductor
The core watchdog timer is available to provide compatibility with the
watchdog timer implemented on previous ColdFire devices. However,
there is a second watchdog timer available on the MCF5271 that has
new features. See
information. Please note that the core watchdog timer is unable to
reset the device. It is only permitted to assert an interrupt. For
resetting the device, use the second watchdog timer.
Chapter 20, “Watchdog Timer
MCF5271 Reference Manual, Rev. 2
NOTE
Module” for more
11-1