MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 359

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

To perform a read or write operation on the MII Management Interface, the MMFR register must
be written by the user. To generate a valid read or write management frame, the ST field must be
written with a 01 pattern, and the TA field must be written with a 10. If other patterns are written
to these fields, a frame will be generated but will not comply with the IEEE 802.3 MII definition.
To generate an IEEE 802.3-compliant MII Management Interface write frame (write to a PHY
register), the user must write {01 01 PHYAD REGAD 10 DATA} to the MMFR register. Writing
this pattern will cause the control logic to shift out the data in the MMFR register following a
preamble generated by the control state machine. During this time the contents of the MMFR
register will be altered as the contents are serially shifted and will be unpredictable if read by the
user. Once the write management frame operation has completed, the MII interrupt will be
generated. At this time the contents of the MMFR register will match the original value written.
To generate an MII Management Interface read frame (read a PHY register) the user must write
{01 10 PHYAD REGAD 10 XXXX} to the MMFR register (the content of the DATA field is a
don’t care). Writing this pattern will cause the control logic to shift out the data in the MMFR
register following a preamble generated by the control state machine. During this time the contents
of the MMFR register will be altered as the contents are serially shifted, and will be unpredictable
if read by the user. Once the read management frame operation has completed, the MII interrupt
will be generated. At this time the contents of the MMFR register will match the original value
written except for the DATA field whose contents have been replaced by the value read from the
PHY register.
If the MMFR register is written while frame generation is in progress, the frame contents will be
altered. Software should use the MII_STATUS register and/or the MII interrupt to avoid writing
to the MMFR register while frame generation is in progress.
Freescale Semiconductor
31–30
29–28
27–23
22–18
17–16
15–0
Bit
Name
DATA
OP
RA
ST
PA
TA
Start of frame delimiter. These bits must be programmed to 01 for a valid MII management
frame.
Operation code. This field must be programmed to 10 (read) or 01 (write) to generate a
valid MII management frame. A value of 11 will produce “read” frame operation while a
value of 00 will produce “write” frame operation, but these frames will not be MII compliant.
PHY address. This field specifies one of up to 32 attached PHY devices.
Register address. This field specifies one of up to 32 registers within the specified PHY
device.
Turn around. This field must be programmed to 10 to generate a valid MII management
frame.
Management frame data. This is the field for data to be written to or read from the PHY
register.
Table 19-9. MMFR Field Descriptions
MCF5271 Reference Manual, Rev. 2
Description
Memory Map/Register Definition
19-15