MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 533

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

For AES, which uses a 128-bit key, SKKDR1–SKKDR4 must be written. For single DES,
SKKDR1–SKKDR2 must be written (56-bit key & 8-bit parity). For 2-key 3DES, SKKDR1–4
must be written. For 3-key 3DES, SKKDR1–6 must be written. The SKKDRn registers are
summarized in
Attempting to read the SKKDRn registers will generate an illegal address error. If the key registers
are modified during message processing, a register modify error will be generated, setting
SKESR[RMDP] and triggering an interrupt to the interrupt controller (if RMDP is not masked).
28.2.1.12 SKHA Context Registers (SKCRn)
Prior to loading key data, the user must write the appropriate initialization data to the SKHA.
Following a done interrupt, the user must read the contents of the SKCRn registers prior to
switching context. These values must be restored to resume processing of the original message.
The SKCRn registers are loaded differently depending on the algorithm and cipher mode. The
location and values are summarized in
in the lowest 32-bit context register.
Ex: 0x0123456789ABCDEF101112131415161718191A1B1C1D1E1F would be loaded as
follows:
Freescale Semiconductor
SKCR1 = 0x0102030405060708090A0B0C0D0E0F
SKCR2 = 0x101112131415161718191A1B1C1D1E1F
Algorithm
3DES
3DES
2 key
3 key
DES
AES
Table
DES-ECB
DES-CBC
AES-ECB
AES-CBC
DES-CTR
Algorithm
/Mode
K1 Bytes 1–4
K1 Bytes 1–4
Bytes 1–4
Bytes 1–4
SKKDR1
28-7.
Table 28-7. SKHA Key Data Register Definitions
Table 28-8. SKHA Context Register Definitions
Counter*
—
—
1
IV*
K1 Bytes 5–8 K2 Bytes 1–4
K1 Bytes 5–8 K2 Bytes 1–4
—
—
Bytes 5–8
Bytes 5–8
SKKDR2
2
IV*
MCF5271 Reference Manual, Rev. 2
—
—
—
—
3
SKHA Context Register n (32-bits each)
Table
—
—
—
—
4
Bytes 9–12
SKKDR3
28-8. Context should be loaded with the lower bytes
—
—
—
—
—
—
5
—
—
—
—
—
6
K2 Bytes 5–8
K2 Bytes 5–8
Bytes 13–16
—
—
—
—
—
SKKDR4
7
—
—
—
—
—
—
8
—
—
—
—
—
9
K3 Bytes 1–4
SKKDR5
10
—
—
—
—
—
—
—
—
Memory Map/Register Definition
11
—
—
—
—
—
K3 Bytes 5–8
12
—
—
—
—
—
SKKDR6
—
—
—
28-15