MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 377

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

DMA of the buffer is complete. In the TxBD the user initializes the R, W, L, and TC bits and the
length (in bytes) in the first longword, and the buffer pointer in the second longword.
The FEC will set the R bit = 0 in the first longword of the BD when the buffer has been DMA’d.
Status bits for the buffer/frame are not included in the transmit buffer descriptors. Transmit frame
status is indicated via individual interrupt bits (error conditions) and in statistic counters in the
MIB block. See
Freescale Semiconductor
Offset + 0
Offset + 2
Offset + 4
Offset + 6
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Word
15
R
Section 19.2.3, “MIB Block Counters Memory
TO1
Bits
8–0
Table 19-29. Transmit Buffer Descriptor Field Definitions
15
14
13
12
10
11
14
9
Figure 19-26. Transmit Buffer Descriptor (TxBD)
W
13
Field Name
ABC
TO1
TO2
TO2
TC
—
W
12
R
L
11
MCF5271 Reference Manual, Rev. 2
L
Ready. Written by the FEC and the user.
0 The data buffer associated with this BD is not ready for transmission. The
1 The data buffer, which has been prepared for transmission by the user, has
Transmit software ownership. This field is reserved for software use. This
read/write bit will not be modified by hardware, nor will its value affect
hardware.
Wrap. Written by user.
0 The next buffer descriptor is found in the consecutive location
1 The next buffer descriptor is found at the location defined in ETDSR.
Transmit software ownership. This field is reserved for use by software. This
read/write bit will not be modified by hardware, nor will its value affect
hardware.
Last in frame. Written by user.
0 The buffer is not the last in the transmit frame.
1 The buffer is the last in the transmit frame.
Tx CRC. Written by user (only valid if L = 1).
0 End transmission immediately after the last data byte.
1 Transmit the CRC sequence after the last data byte.
Append bad CRC. Written by user (only valid if L = 1).
0 No effect
1 Transmit the CRC sequence inverted after the last data byte (regardless of
Reserved.
user is free to manipulate this BD or its associated data buffer. The FEC
clears this bit after the buffer has been transmitted or after an error
condition is encountered.
not been transmitted or is currently being transmitted. No fields of this BD
may be written by the user once this bit is set.
TC value).
TC
10
Tx Data Buffer Pointer - A[31:16]
Tx Data Buffer Pointer - A[15:0]
ABC
9
Data Length
—
8
—
7
Description
—
6
Map” for more details.
—
5
—
4
Memory Map/Register Definition
—
3
—
2
—
1
—
0
19-33