MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 364

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Fast Ethernet Controller (FEC)
19.2.4.11 Physical Address Low Register (PALR)
The PALR is written by the user. This register contains the lower 32 bits (bytes 0,1,2,3) of the
48-bit address used in the address recognition process to compare with the DA (Destination
Address) field of receive frames with an individual DA. In addition, this register is used in bytes
0 through 3 of the 6-byte source address field when transmitting PAUSE frames. This register is
not reset and must be initialized by the user.
19.2.4.12 Physical Address High Register (PAUR)
The PAUR is written by the user. This register contains the upper 16 bits (bytes 4 and 5) of the
48-bit address used in the address recognition process to compare with the DA (destination
address) field of receive frames with an individual DA. In addition, this register is used in bytes 4
and 5 of the 6-byte Source Address field when transmitting PAUSE frames. Bits 15:0 of PAUR
contain a constant type field (0x8808) used for transmission of PAUSE frames. This register is not
reset and bits 31:16 must be initialized by the user.
19-20
Address
Reset
Reset
31–0
Bits
W
W
R
R
—
—
31
15
PADDR1
Name
—
—
30
14
Figure 19-12. Physical Address Low Register (PALR)
—
—
29
13
Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8) and 3 (bits 7:0) of the 6-byte individual
address to be used for exact match, and the source address field in PAUSE frames.
—
—
28
12
Table 19-15. PALR Field Descriptions
—
—
27
11
MCF5271 Reference Manual, Rev. 2
—
—
26
10
25
—
—
9
IPSBAR + 0x10E4
PADDR1
—
PADDR1
—
24
8
23
—
—
Description
7
—
—
22
6
—
—
21
5
—
—
20
4
—
—
19
3
Freescale Semiconductor
—
—
18
2
—
—
17
1
16
—
—
0