MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 151

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Please note that the frequency modulation system is dependent upon several factors. The
accuracies of the VDDPLL/VSSPLL voltage, of the crystal oscillator frequency, and of the
manufacturing variation.
For example, if a 5% accurate supply voltage is utilized, then a 5% modulation depth error will
result. If the crystal oscillator frequency is skewed from 8MHz, the resulting modulation
frequency will be proportionally skewed. Finally, the error due to the manufacturing and
environment variation alone can cause the frequency modulation depth error to be greater than
20%.
Freescale Semiconductor
4. Write a value of RFD = RFD + 1 to the RFD field of the SYNCR to ensure the maximum
5. Program the desired modulation rates and depths to the RATE and DEPTH fields in the
6. Allow time for the calibration sequence. Wait for the PLL to lock (the LOCK bit to set in
system frequency is not exceeded during the calibration routine.
SYNCR. This action initiates the calibration sequence.
the SYNSR). At this time CALDONE should be asserted. CALPASS will be asserted if
the calibration was successful. If not, the calibration can be re-initiated by repeating from
step 2. When the PLL achieves lock, write the desired RFD value.
F
F
max
min
f
Fmax = f
Fmin = f
Fmod = Fref/Q where Q = {40, 80}
Figure 7-6. Frequency Modulation Waveform
sys/2
sys/2
MCF5271 Reference Manual, Rev. 2
∆Fm
+ {1%, 2%}
- {1%, 2%}
∆t
=
----------- -
F
mod
1
∆Fm
Functional Description
t
7-17