MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 274

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

DMA Controller Module
14.3.5 DMA Control Registers (DCR0–DCR3)
DCRn, shown in
14-10
Address
Reset
Reset
Bits
Bits
W
W
R INT EEXT
R
31
30
1
0
31
15
0
0
30
14
0
0
DONE
Name
Name
EEXT
SMOD
BSY
Figure
INT
CS
29
13
Table 14-3. DSRn Field Descriptions (Continued)
0
0
14-8, is used for configuring the DMA controller module.
Busy
0 DMA channel is inactive. Cleared when the DMA has finished the last transaction.
1 BSY is set the first time the channel is enabled after a transfer is initiated.
Transactions done. Set when all DMA controller transactions complete, as determined by
transfer count or error conditions. When BCR reaches zero, DONE is set when the final
transfer completes successfully. DONE can also be used to abort a transfer by resetting
the status bits. When a transfer completes, software must clear DONE before
reprogramming the DMA.
0 Writing or reading a 0 has no effect.
1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and can be
Figure 14-8. DMA Control Registers (DCRn)
Interrupt on completion of transfer. Determines whether an interrupt is generated by
completing a transfer or by the occurrence of an error condition.
0 No interrupt is generated.
1 Internal interrupt signal is enabled.
Enable external request. Care should be taken because a collision can occur between the
START bit and DREQn when EEXT = 1.
0 External request is ignored.
1 Enables external request to initiate transfer. The internal request (initiated by setting the
AA
28
12
used in an interrupt handler to clear the DMA interrupt and error bits.
START bit) is always enabled.
0
0
Table 14-4. DCRn Field Descriptions
IPSBAR + 0x00_010C (DMA0); IPSBAR + 0x011C (DMA1);
IPSBAR + 0x012C (DMA2); IPSBAR + 0x013C (DMA3)
27
11
0
0
MCF5271 Reference Manual, Rev. 2
BWC
26
10
0
0
DMOD
25
0
0
9
24
0
0
0
8
D_REQ
23
0
0
0
7
Description
Description
SINC
22
0
0
0
6
21
LINKCC
0
0
5
SSIZE
20
0
0
4
DINC
19
0
0
3
LCH1
Freescale Semiconductor
18
0
0
2
DSIZE
17
0
0
1
LCH2
START
16
0
0
0
0