MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 547

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

29.4.3.1 EXTEST Instruction
The external test (EXTEST) instruction selects the boundary scan register. It forces all output pins
and bidirectional pins configured as outputs to the values preloaded with the
SAMPLE/PRELOAD instruction and held in the boundary scan update registers. EXTEST can
also configure the direction of bidirectional pins and establish high-impedance states on some
pins. EXTEST asserts internal reset for the MCU system logic to force a predictable internal state
while performing external boundary scan operations.
29.4.3.2 IDCODE Instruction
The IDCODE instruction selects the 32-bit IDCODE register for connection as a shift path
between the TDI and TDO pin. This instruction allows interrogation of the MCU to determine its
version number and other part identification data. The shift register lsb is forced to logic 1 on the
rising edge of TCLK following entry into the capture-DR state. Therefore, the first bit to be shifted
out after selecting the IDCODE register is always a logic 1. The remaining 31 bits are also forced
to fixed values on the rising edge of TCLK following entry into the capture-DR state.
IDCODE is the default instruction placed into the instruction register when the TAP resets. Thus,
after a TAP reset, the IDCODE register is selected automatically.
29.4.3.3 SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction has two functions:
Freescale Semiconductor
ACCESS_AUX_TAP_eTPU
• PRELOAD - initialize the boundary scan register update cells before selecting EXTEST or
1
Freescale reserves the right to change the decoding of the unused opcodes in the future.
ENABLE_TEST_CTRL
CLAMP. This is achieved by ignoring the data shifting out on the TDO pin and shifting in
initialization data. The update-DR state and the falling edge of TCLK can then transfer this
Instruction
Reserved
BYPASS
EXTEST
CLAMP
HIGHZ
Table 29-5. JTAG Instructions (Continued)
all others
IR[4:0]
00100
00110
01001
01100
10000
11111
MCF5271 Reference Manual, Rev. 2
Selects boundary scan register while applying fixed values to output pins and
asserting functional reset
Selects TEST_CTRL register
Selects bypass register while tri-stating all output pins and asserting
functional reset
Selects bypass while applying fixed values to output pins and asserting
functional reset
Enables access to the eTPU Nexus TAP controller
Selects bypass register for data operations
Decoded to select bypass register
Instruction Summary
1
Functional Description
29-9