MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 414

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

DMA Timers (DTIM0–DTIM3)
22.2.8 DMA Timer Event Registers (DTERn)
DTERn, shown in
DTERn[REF]. This reporting is done regardless of the corresponding DMA request or interrupt
enable values, DTXMRn[DMAEN] and DTMRn[ORRI,CE].
Writing a 1 to either DTERn[REF] or DTERn[CAP] clears it (writing a 0 does not affect bit value);
both bits can be cleared at the same time. If configured to generate an interrupt request, the REF
and CAP bits must be cleared early in the interrupt service routine so the timer module can negate
the interrupt request signal to the interrupt controller. If configured to generate a DMA request, the
processing of the DMA data transfer automatically clears both the REF and CAP flags via the
internal DMA ACK signal.
22-6
Bits
6–1
0
MODE16
Name
Address
—
Figure
Reset
Table 22-3.
Figure 22-4. DMA Timer Event Registers (DTERn)
W
R
Reserved, should be cleared.
Selects the increment mode for the timer. MODE16 = 1 is intended to exercise the upper
0 Increment timer by 1
1 Increment timer by 65,537
22-4, reports capture or reference events by setting DTERn[CAP] or
bits of the 32-bit timer in diagnostic software without requiring the timer to count through
its entire dynamic range. When set, the counter’s upper 16 bits mirror its lower 16 bits.
All 32 bits of the counter are still compared to the reference value.
IPSBAR + 0x00_0403 (DTER0); IPSBAR + 0x00_0443 (DTER1);
0
0
IPSBAR + 0x00_0483 (DTER2); IPSBAR + 0x00_04C3 (DTER3)
7
DTXMR
MCF5271 Reference Manual, Rev. 2
0
0
6
0
0
n Field Descriptions (Continued)
5
0
0
4
Description
0
0
3
2
0
0
REF
w1c
0
1
CAP
w1c
0
0
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