MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 286

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Edge Port Module (EPORT)
In wait and doze modes, the EPORT module continues to operate as it does in run mode. It may
be configured to exit the low-power modes by generating an interrupt request on either a selected
edge or a low level on an external pin. In stop mode, there are no clocks available to perform the
edge-detect function. Only the level-detect logic is active (if configured) to allow any low level on
the external interrupt pin to generate an interrupt (if enabled) to exit stop mode.
15.3
All pins default to general-purpose input pins at reset. The pin value is synchronized to the rising
edge of CLKOUT when read from the EPORT pin data register (EPPDR). The values used in the
edge/level detect logic are also synchronized to the rising edge of CLKOUT. These pins use
Schmitt triggered input buffers which have built in hysteresis designed to decrease the probability
of generating false edge-triggered interrupts for slow rising and falling input signals.
When a pin is configured as an output, it is driven to a state whose level is determined by the
corresponding bit in the EPORT data register (EPDR). All bits in the EPDR are high at reset.
15.4
This subsection describes the memory map and register structure. Refer to
description of the EPORT memory map. The EPORT has an IPSBAR offset for base address of
0x0013_0000.
15-2
Low-power Mode
Interrupt/General-Purpose I/O Pin Descriptions
Memory Map/Register Definition
Doze
The low-power interrupt control register (LPICR) in the System
Control Module specifies the interrupt level at or above which is
needed to bring the device out of a low-power mode.
Wait
Stop
The input pin synchronizer is bypassed for the level-detect logic since
no clocks are available.
Table 15-1. Edge Port Module Operation in Low-power Modes
Level-sensing Only
EPORT Operation
MCF5271 Reference Manual, Rev. 2
Normal
Normal
NOTE
NOTE
Any IRQn Interrupt at or above level in LPICR
Any IRQn Interrupt at or above level in LPICR
Any IRQn Interrupt set for level-sensing at or
above level in LPICR
Mode Exit
Freescale Semiconductor
Table 15-2
for a