MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 417

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

22.3
The general-purpose timer modules are typically used in the following manner, though this is not
necessarily the program order in which these actions must occur:
Freescale Semiconductor
• The DTMRn and DTXMRn registers are configured for the desired function and behavior.
• The DTMRn[CLK] register is configured to select the clock source to be routed to the
• The 8-bit DTMRn[PS] prescaler value is set
• Using DTMRn[RST] the counter is cleared and started
• Timer events are either handled with an interrupt service routine, a DMA request, or by a
Address
Reset
Reset
— Count and compare to a reference value stored in the DTRRn register
— Capture the timer value on an edge detected on DTINn
— Configure DTOUTn output mode
— Increment counter by 1 or by 65,537 (16-bit mode)
— Enable/disable interrupt or DMA request on counter reference match or capture edge
prescaler.
— System clock (can be divided by 1 or 16)
— DTINn, the maximum value of DTINn is 1/5 of the system clock, as described in the
software polling mechanism
W
W
R
R
Using the DMA Timer Modules
MCF5271 Electrical Characteristics.
31
15
0
0
DTINn may not be configured as a clock source when the timer
capture mode is selected or indeterminate operation will result.
30
14
0
0
29
13
0
0
Figure 22-7. DMA Timer Counters (DTCNn)
IPSBAR + 0x00_040C (DTCN0); IPSBAR + 0x00_044C (DTCN1);
IPSBAR + 0x00_048C (DTCN2); IPSBAR + 0x00_04CC (DTCN3)
28
12
0
0
27
11
0
0
MCF5271 Reference Manual, Rev. 2
CNT (32-bit timer counter value count)
CNT (32-bit timer counter value count)
26
10
0
0
25
0
0
9
NOTE
24
0
0
8
23
0
0
7
22
0
6
0
21
0
0
5
20
0
0
4
Using the DMA Timer Modules
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0
22-9