MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 152

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Clock Module
7.4.5
The frequency modulation calibration system tunes a reference current into the modulation D/A
so that the modulation depth (F
should be disabled prior to making a change to either the MFD, DEPTH, or RATE. Upon enabling
frequency modulation a new calibration sequence is performed. A change to MFD, DEPTH, or
RATE while in modulation will invalidate calibration results.
Entering the FM calibration mode requires the user to program the EXP field of the SYNCR.
Values for EXP can be found using the following equation:
Example:
This routine will correct for process variations, but as temperature can change after the calibration
has been performed, variation due to temperature drift is not eliminated. This system is also
voltage dependent, so if supply voltages change after the sequence takes place, error incurred will
not be corrected. The calibration system reuses the two counters in the lock detect circuit: the
reference and feedback counters. The reference counter is still clocked by the reference clock, but
the feedback counter is clocked by the ICO clock.
When the calibration routine is initiated (writing to the DEPTH bits), the CALPASS status bit is
immediately set and the CALDONE status bit is immediately cleared.
When calibration is induced the ICO is given time to settle. Then both the feedback and reference
counters start counting. Full ICO clock cycles are counted by the feedback counter during this time
to give the initial center frequency count. When the reference counter has counted to the
programmed number of reference count cycles, the input to the feedback counter is disabled and
the result is placed in the COUNT0 register. The calibration system then enables modulation at
programmed ∆F
feedback counter begins to count full ICO clock cycles again to obtain the delta-frequency count.
When the reference counter has counted to the new programmed number of reference count cycles,
the feedback counter is stopped again.
The delta-frequency count minus the center frequency count (COUNT0) results in a delta count
proportional to the reference current into the modulation D/A. That delta count is subtracted from
the expected value given in the EXP field of the SYNCR register resulting in an error count. The
7-18
For the value of MFD = 4, the number of reference clock cycles to be counted (M) would
be 480. Refer to
based on MFD setting. To obtain a percent modulation (P) of 1%, the EXP field would have
to be set at:
Rounding this value to the closest integer yields the value of 58 that should be entered into
the EXP field for this example.
Frequency Modulation Depth Calibration
m
. The ICO is given time to settle. Both counters are reset and restarted. The
EXP
Figure 7-8
=
(
2× 4
max
(
MCF5271 Reference Manual, Rev. 2
for a complete list of values to be used for the variable (M)
+
and F
EXP
2
)×480×1
min
=
(
------------------------------------------------------- -
2× MFD
) remains within specification. Frequency modulation
) 100
(
⁄
100
=
+
57.6
2
)×M×P
)
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