MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 235

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

12.3.1.5.2 External Bus Control Pin Assignment Register (PAR_BUSCTL)
The PAR_BUSCTL register controls the functions of the external bus control signal pins.
Freescale Semiconductor
1
Address
The selection between the address function and chip select function on each of the A[23:21] pins is determined by the
value of the RCSC field in the CIM reset configuration register.
1
Reset
Bits
7–5
4–1
Note if the port size of the external boot device is 8-bit or 16-bit, and the port size of the external SDRAM is 32-bit,
the PAR_AD register must be written after reset to enable the primary functions on the D[15:0] pins before any
SDRAM accesses are attempted.
0
Master mode
W
R
Operation
Mode of
Figure 12-31. External Bus Control Pin Assignment (PAR_BUSCTL)
15
0
0
PAR_DATAL The PAR_DATAL bit configures the D[15:0] pins for their primary functions or GPIO.
PAR_ADDR
PAR_
Name
OE
14
1
—
External Boot
13
0
0
Port Size of
Device
The PAR_ADDR bits configure each of the A[23:21] pins for one of their primary functions
16-bit
32-bit
or GPIO.
0 A[23:21] pin configured for GPIO
1 A[23:21] pin configured for address bit 23–21 function or CS[6:4] function
Reserved, should be cleared.
0 D[15:0] pins configured for GPIO
1 D[15:0] pins configured for data 15-0 functions
Table 12-8. Reset Values for PAR_AD Bits
8-bit
PAR_
Table 12-9. PAR_AD Field Descriptions
TA
12
1
1
PAR_TEA
11
1
MCF5271 Reference Manual, Rev. 2
PAR_ADDR23
Reset Value
10
1
1
1
1
9
0
0
IPSBAR + 0x10_0042
PAR_
RWB
1
8
PAR_ADDR22
Reset Value
7
0
0
Description
1
1
1
TSIZ1
PAR_
1
6
0
0
5
PAR_ADDR21
Reset Value
TSIZ0
PAR_
1
4
1
1
1
Memory Map/Register Definition
PAR_TS
3
1
PAR_DATAL
Reset Value
1
2
1
0
0
1
PAR_TIP
1
1
1
0
12-19