MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 321

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

18.1.2 Overview
The synchronous DRAM controller module provides glueless integration of SDRAM with the
ColdFire product. The key features of the DRAM controller include the following:
18.1.2.1 Definitions
The following terminology is used in this chapter:
18.1.3 Operation
By running synchronously with the system clock, SDRAM can (after an initial latency period) be
accessed on every clock; 5-1-1-1 is a typical MCF5271 burst rate to the SDRAM.
Note that because the MCF5271 cannot have more than one page open at a time, it does not support
interleaving.
SDRAM controllers are more sophisticated than asynchronous DRAM controllers. Not only must
they manage addresses and data, but they must send special commands for such functions as
precharge, read, write, burst, auto-refresh, and various combinations of these functions.
lists common SDRAM commands.
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• Support for two independent blocks of SDRAM
• Interface to standard SDRAM components
• Programmable SD_SRAS, SD_SCAS, and refresh timing
• Support for 8-, 16-, and 32-bit wide SDRAM blocks
• SDRAM block: Any group of DRAM memories selected by one of the MCF5271
• SDRAM: RAMs that operate like asynchronous DRAMs but with a synchronous clock, a
• SDRAM bank: An internal partition in an SDRAM device. For example, a 64-Mbit
Command
SD_SRAS[1:0] signals. Thus, the MCF5271 can support two independent memory blocks.
The base address of each block is programmed in the DRAM address and control registers
(DACR0 and DACR1).
pipelined, multiple-bank architecture, and a faster speed.
SDRAM component might be configured as four 512K x 32 banks. Banks are selected
through the SDRAM component’s bank select lines.
ACTV
MRS
NOP
Activate. Executed before
Mode register set.
No-op. Does not affect SDRAM state machine; DRAM controller control signals negated; SD_CS[1:0]
asserted.
Table 18-1. SDRAM Commands
MCF5271 Reference Manual, Rev. 2
READ
or
WRITE
executes; SDRAM registers and decodes row address.
Definition
Table 18-1
Introduction
18-3