MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 446

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

UART Modules
24.3.3
The USRn registers, shown in
FIFO.
24-8
Bits
3–0
4
UART Status Registers (USRn)
TxCTS
Name
SB
Address
Reset
Table 24-4. UMR2n Field Descriptions (Continued)
W
Transmitter clear-to-send. If both TxCTS and TxRTS are enabled, TxCTS controls the operation
of the transmitter.
0 UnCTS has no effect on the transmitter.
1 Enables clear-to-send operation. The transmitter checks the state of UnCTS each time it is
Stop-bit length control. Selects the length of the stop bit appended to the transmitted character.
Stop-bit lengths of 9/16 to 2 bits are programmable for 6–8 bit characters. Lengths of 1-1/16 to
2 bits are programmable for 5-bit characters. In all cases, the receiver checks only for a high
condition at the center of the first stop-bit position, that is, one bit time after the last data bit or
after the parity bit, if parity is enabled. If an external 1x clock is used for the transmitter, clearing
bit 3 selects one stop bit and setting bit 3 selects two stop bits for transmission.
R
ready to send a character. If UnCTS is asserted, the character is sent; if it is deasseted, the
channel UnTXD remains in the high state and transmission is delayed until UnCTS is
asserted. Changes in UnCTS as a character is being sent do not affect its transmission.
Figure 24-5. UART Status Register (USRn)
RB
0
7
Figure
IPSBAR + 0x0204 (USR0); IPSBAR + 0x0244 (USR1);
FE
MCF5271 Reference Manual, Rev. 2
0
6
0000
0001
0010
0011
0100
0101
0110
24-5, show the status of the transmitter, the receiver, and the
0111
SB
PE
0
5
IPSBAR + 0x0284 (USR2)
5 Bits
1.063
1.125
1.188
1.250
1.313
1.375
1.438
1.500
OE
0
4
6–8 Bits
TXEMP TXRDY FFULL RXRDY
0.563
0.625
0.688
0.750
0.813
0.875
0.938
1.000
Description
0
3
2
0
1000
1001
1010
1011
1100
1101
1110
1111
SB
0
1
5–8 Bits
1.563
1.625
1.688
1.750
1.813
1.875
1.938
2.000
0
0
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