MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 226

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

General Purpose I/O Module
12.3.1 Register Descriptions
12.3.1.1 Port Output Data Registers (PODR_x)
The PODR_x registers store the data to be driven on the corresponding port pins when the pins are
configured for general purpose output. The PODR_x registers are each 8 bits wide, but not all ports
use all 8 bits. The register definitions for all ports are shown in
The PODR_x registers are read/write. At reset, all implemented bits in the PODR_x registers are
set. Reserved bits always remain cleared.
12-10
1
0x10_0020
0x10_0024
0x10_0028
0x10_0030
0x10_0034
0x10_0038
0x10_0040
0x10_0044
0x10_0048
0x10_0054
0x10_0058
0x10_007F
IPSBAR
S/U = supervisor or user mode access.
0x002C
0x003C
0x004C
0x0050
Offset
–
Table 12-3. MCF5271 Ports Module Memory Map (Continued)
PPDSDR_UARTH
PPDSDR_ADDR
PCLRR_UARTH
PCLRR_ADDR
PPDSDR_BS
DSCR_QSPI
PCLRR_BS
DSCR_EIM
PAR_AD
PAR_BS
[31:24]
PAR_TIMER
PAR_UART
PPDSDR_UARTL
PPDSDR_DATAH
MCF5271 Reference Manual, Rev. 2
PCLRR_DATAH
PCLRR_UARTL
Port Clear Output Data Registers
Drive Strength Control Registers
Port Pin Data/Set Data Registers
DSCR_TIMER
PPDSDR_CS
Port Pin Assignment Registers
PCLRR_CS
Reserved
Reserved
PAR_CS
[23:16]
2
2
Reserved
Reserved
Reserved
PPDSDR_SDRAM
PPDSDR_DATAL
PCLRR_SDRAM
PPDSDR_QSPI
PCLRR_DATAL
DSCR_FECI2C
2
PCLRR_QSPI
2
2
PAR_SDRAM
PAR_QSPI
[15:8]
PAR_BUSCTL
Reserved
Reserved
Figure 12-2
PPDSDR_BUSCTL
PPDSDR_FECI2C
PPDSDR_TIMER
PCLRR_BUSCTL
PCLRR_FECI2C
PCLRR_TIMER
2
2
PAR_FECI2C
DSCR_UART
Reserved
[7:0]
through
Freescale Semiconductor
2
Figure
Access
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
1
12-7.