MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 430

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Queued Serial Peripheral Interface (QSPI) Module
23-10
Address
Reset
13–10
Bits
W
7–0
R MSTR DOHIE
15
14
9
8
15
0
DOHIE
MSTR
Name
CPOL
CPHA
BAUD
BITS
14
0
13
0
Master mode enable.
0 Reserved, do not use.
1 The QSPI is in master mode. Must be set for the QSPI module to operate correctly.
Data output high impedance enable. Selects QSPI_DOUT mode of operation.
0 Default value after reset. QSPI_DOUT is actively driven between transfers.
1 QSPI_DOUT is high impedance between transfers.
Transfer size. Determines the number of bits to be transferred for each entry in the queue.
Clock polarity. Defines the clock polarity of QSPI_CLK.
0 The inactive state value of QSPI_CLK is logic level 0.
1 The inactive state value of QSPI_CLK is logic level 1.
Clock phase. Defines the QSPI_CLK clock-phase.
0 Data captured on the leading edge of QSPI_CLK and changed on the following edge of
1 Data changed on the leading edge of QSPI_CLK and captured on the following edge of
Baud rate divider. The baud rate is selected by writing a value in the range 2–255. A value
of zero disables the QSPI. A value of 1 is an invalid setting. The desired QSPI_CLK baud
rate is related to the internal bus clock and QMR[BAUD] by the following expression:
QMR[BAUD] = f
Figure 23-3. QSPI Mode Register (QMR)
QSPI_CLK.
QSPI_CLK.
12
0
Table 23-4. QMR Field Descriptions
BITS
11
0
MCF5271 Reference Manual, Rev. 2
sys/2
10
0
0001–0111
/ (2 × [desired QSPI_CLK baud rate])
CPOL CPHA
IPSBAR + 0x00_0340
0
9
BITS
0000
1000
1001
1010
1011
1100
1101
1110
1111
1
8
Description
Bits per Transfer
0
7
Reserved
16
10
11
12
13
14
15
0
8
9
6
0
5
4
0
BAUD
0
3
Freescale Semiconductor
1
2
0
1
0
0