MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 320

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Synchronous DRAM Controller Module
The DRAM controller’s major components are as follows:
18-2
• DRAM address and control registers (DACR0 and DACR1): The DRAM controller
• Control logic and state machine: Generates all SDRAM signals, taking hit information and
• Hit logic: Compares address and attribute signals of a current SDRAM bus cycle to both
• Address multiplexing: Multiplexes addresses to allow column and row addresses to share
• Data Generation: Controls the data input and data output transmission between the
Internal
Q[31:0] internal
A[31:0]
D[31:0] internal
Bus
consists of two configuration register units, one for each supported memory block. DACR0
is accessed at IPSBAR + 0x00_0048; DACR1 is accessed at IPSBAR + 0x00_0050. The
register information is passed on to the hit logic.
bus-cycle characteristic data from the block logic in order to generate SDRAM accesses.
Handles refresh requests from the refresh counter.
— DRAM control register (DCR): Contains data to control refresh operation of the DRAM
— Refresh counter: Determines when refresh should occur; controlled by the value of
DACRs to determine if an SDRAM block is being accessed. Hits are passed to the control
logic along with characteristics of the bus cycle to be generated.
pins. This allows glueless interface to SDRAMs.
on-platform and off-platform data buses.
controller. Both memory blocks are refreshed concurrently as controlled by DCR[RC].
DCR[RC]. It generates a refresh request to the control block.
DRAM Controller Module
Figure 18-1. Synchronous DRAM Controller Block Diagram
DRAM Address/Control Register 0
DRAM Address/Control Register 1
Memory Block 0 Hit Logic
Memory Block 1 Hit Logic
(DACR0)
(DACR1)
MCF5271 Reference Manual, Rev. 2
Refresh Counter
Register (DCR)
DRAM Control
State Machine
Control Logic
Multiplexing
Generation
Address
Data
and
D[31:0]
A[23:0]
Q[31:0]
SD_CS[1:0]
SD_SCAS
SD_SRAS
SD_CKE
SD_WE
BS[3:0]
OE
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