MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 305

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

17.4 Bus Errors
Attempting to write to a range of addresses that is write protected (CSARn[WP] = 1) will not
assert the corresponding chip select. Also, an access error exception will occur. See
Section 16.4.1.2, “Chip Select Mask Registers (CSMR0–CSMR7)”
Exceptions”
17.5 Data Transfer Operation
Data transfers between the MCF5271 and other devices involve the following signals:
The address bus, write data, TS, and all attribute signals change on the rising edge of CLKOUT.
Read data is latched into the MCF5271 on the rising edge of CLKOUT.
The MCF5271 bus supports byte, word, and longword operand transfers and allows accesses to 8-,
16-, and 32-bit data ports. Aspects of the transfer, such as the port size, the number of wait states
for the external slave being accessed, and whether internal transfer termination is enabled, can be
programmed in the chip-select control registers (CSCRs) and the DRAM control registers
(DACRs).
Freescale Semiconductor
• Address bus (A[23:0])
• Data bus (D[31:0])
• Control signals (TS and TA)
• CSn, OE, BSn
• Attribute signals (R/W, TSIZ, and TIP)
Falling-Edge
Rising-Edge
CLKOUT
Signals
Signals
Inputs
t
t
t
t
vo
ho
si
hi
=Required input setup time relative to CLKOUT edge
=Required input hold time relative to CLKOUT edge
Figure 17-1. Signal Relationship to CLKOUT for Non-DRAM Access
=Propagation delay of signal relative to CLKOUT edge
=Output hold time relative to CLKOUT edge
for more details.
t
si
MCF5271 Reference Manual, Rev. 2
t
t
vo
hi
t
vo
t
and
ho
Section 3.7, “Processor
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Bus Errors
17-3