MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 513

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Chapter 27
Random Number Generator (RNG)
27.1
This chapter describes the Random Number Generator (RNG), including a programming model,
functional description, and application information.
27.1.1 Overview
The Random Number Generator (RNG) module is capable of generating 32-bit random numbers.
It is designed to comply with FIPS-140 standards for randomness and non-determinism. The
random bits are generated by clocking shift registers with clocks derived from ring oscillators. The
configuration of the shift registers ensures statistically good data (i.e. data that looks random). The
oscillators with their unknown frequencies provide the required entropy needed to create random
data.
27.2
The address map for the RNG module is shown in
found in the following section.
27.2.1 RNG Control Register (RNGCR)
Immediately following reset, the RNG begins generating entropy in its internal shift registers.
Random data is not pushed to the output FIFO until after the GO bit in the RNGCR is set to a one.
After this, a random 32-bit word is pushed to the FIFO every 256 cycles. If the FIFO is full, then
no push will occur.
In this way the FIFO will be kept as close to full as possible. The fields in the RNGCR are defined
in
Freescale Semiconductor
Table
27-2.
Introduction
Memory Map/Register Definition
IPSBAR Offset
0x1A_000C
0x1A_0000
0x1A_0004
0x1A_0008
Mnemonic
RNGOUT
RNGCR
RNGSR
RNGER
Table 27-1. RNG Module Memory Map
MCF5271 Reference Manual, Rev. 2
[31:24]
RNG Entropy Register
RNG Control Register
[23:16]
RNG Status Register
RNG Output FIFO
Table
27-1. Detailed register descriptions are
[15:8]
[7:0]
Access
R/W
W
R
R
27-1