MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 201

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

11.2.1 Register Descriptions
11.2.1.1 Internal Peripheral System Base Address Register (IPSBAR)
The IPSBAR specifies the base address for the 1 Gbyte memory space associated with the on-chip
peripherals. At reset, the base address is loaded with a default location of 0x4000_0000 and
marked as valid (IPSBAR[V]=1). If desired, the address space associated with the internal
modules can be moved by loading a different value into the IPSBAR at a later time.
If an address “hits” in overlapping memory regions, the following priority is used to determine
what memory is accessed:
See
Freescale Semiconductor
1. IPSBAR
2. RAMBAR
3. Cache
4. SDRAM
5. Chip Selects
Figure 11-1
This is the list of memory access priorities when viewed from the
processor core.
1
2
0x00_003C
0x00_0030
0x00_0034
0x00_0038
and
IPSBAR
The LPICR register is described in
The DMAREQC register is described in
Offset
Table 11-2
Table 11-1. SCM Register Map (Continued)
GPACR
[31:24]
—
—
—
for descriptions of the bits in IPSBAR.
MCF5271 Reference Manual, Rev. 2
[23:16]
Chapter 8, “Power
NOTE
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—
—
Chapter 14, “DMA Controller
[15:8]
Management."
—
—
—
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Module.”
[7:0]
Memory Map/Register Definition
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11-3