MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 279

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

14.4.3 Channel Initialization and Startup
Before a block transfer starts, channel registers must be initialized with information describing
configuration, request-generation method, and the data block.
14.4.3.1 Channel Prioritization
The four DMA channels are prioritized in ascending order (channel 0 having highest priority and
channel 3 having the lowest) or in an order determined by DCRn[BWC]. If the BWC encoding for
a DMA channel is 000, that channel has priority only over the channel immediately preceding it.
For example, if DCR3[BWC] = 000, DMA channel 3 has priority over DMA channel 2 (assuming
DCR2[BWC] ≠ 000) but not over DMA channel 1.
If DCR0[BWC] = DCR1[BWC] = 000, DMA0 still has priority over DMA1. In this case,
DCR1[BWC] = 000 does not affect prioritization.
Simultaneous external requests are prioritized either in ascending order or in an order determined
by each channel’s DCRn[BWC] bits.
14.4.3.2 Programming the DMA Controller Module
Note the following general guidelines for programming the DMA:
The DMAREQC register is configured to assign peripheral DMA requests or external DMA
request signals to the individual DMA channels.
The SARn is loaded with the source (read) address. If the transfer is from a peripheral device to
memory, the source address is the location of the peripheral data register. If the transfer is from
memory to either a peripheral device or memory, the source address is the starting address of the
data block. This can be any aligned byte address.
Freescale Semiconductor
• Dual-address write—The DMA controller drives the DARn value onto the address bus. If
• No mechanism exists within the DMA module itself to prevent writes to control registers
• If the DCRn[BWC] value of sequential channels are equal, the channels are prioritized in
DCRn[DINC] is set, DARn increments by the appropriate number of bytes at the
completion of a successful write cycle. BCRn decrements by the appropriate number of
bytes. DSRn[DONE] is set when BCRn reaches zero. If the BCRn is greater than zero,
another read/write transfer is initiated. If the BCRn is a multiple of DCRn[BWC], the DMA
request signal is negated until termination of the bus cycle to allow the internal arbiter to
switch masters.
If a termination error occurs, DSRn[BED,DONE] are set and DMA transactions stop.
during DMA accesses.
ascending order.
MCF5271 Reference Manual, Rev. 2
Functional Description
14-15