MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 148

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Clock Module
7.4.2
In external clock mode, the system is static and does not recognize reset until clocks are applied
to EXTAL and XTAL.
In PLL mode, the PLL operates in self-clocked mode (SCM) during reset until the input reference
clock to the PLL begins operating within the limits given in the electrical specifications.
If a PLL failure causes a reset, the system enters reset using the reference clock. Then the system
clock source changes to the PLL operating in SCM. If SCM is not functional, the system becomes
static. Alternately, if the LOCEN bit in SYNCR is cleared when the PLL fails, the system becomes
static. If external reset is asserted, the system cannot enter reset unless the PLL is capable of
operating in SCM.
7.4.2.1
When a POR is detected, the PLL registers will be initialized to their default state. The PLL will
not begin operating until the VDDPLL POR signal has negated. At this point, the PLL will begin
operating in SCM until a valid reference clock becomes present as indicated by the loss-of-clock
circuit. Refer to
7-14
1
Normal PLL clock mode
1:1 PLL clock mode
External clock mode
f
f
MFD ranges from 0 to 7
RFD ranges from 0 to 7
f
∆F
ref
sys/2
ref
System Clock Mode
Clock Operation During Reset
m
= input reference frequency
in external clock mode must not exceed 150MHz
Power-On Reset (POR)
= CLKOUT frequency
=
f
sys/2
Section 10.4.1.1, “Power-On
×
k
where k = 2±0.6, 4±0.6, or 6±0.6%.
Table 7-8. Clock Out and Clock In Relationships
f
- without frequency modulation
enabled:
- with frequency modulation:
f
sys/2
sys/2
f
f
sys
sys
= 2 × f
= f
MCF5271 Reference Manual, Rev. 2
=
=
ref
2f
------------------------------------------ -
PLL Options
f
-------------------------------------------------------- -
ref
ref
ref_1:1
× MFD
× MFD
(
2
(
RFD
2
RFD
+
Reset,” for more information.
+
2
1
2
) ∆F
)
±
m
Section 7.1.3.1, “Normal PLL Mode with
Crystal Reference”
“Normal PLL Mode with External Reference”
Section 7.1.3.3, “1:1 PLL Mode”
Section 7.1.3.4, “External Clock Mode
(Bypass Mode)”
Cross-Reference
and
Section 7.1.3.2,
Freescale Semiconductor