MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 306

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

External Interface Module (EIM)
Figure 17-2
transfers if a longword is transferred for three port sizes. For example, an 8-bit memory should be
connected to D[31:24] (BS3). A longword transfer takes four transfers on D[31:24], starting with
the MSB and going to the LSB.
The timing relationship of chip selects (CS[7:0]), byte selects (BS[3:0]), and output enable (OE)
with respect to CLKOUT is similar in that all transitions occur during the low phase of CLKOUT.
However, due to differences in on-chip signal routing, signals may not assert simultaneously.
17.5.1 Bus Cycle Execution
When a bus cycle is initiated, the MCF5271 first compares the address of that bus cycle with the
base address and mask configurations programmed for chip selects 0–7 (configured in
CSCR0–CSCR7) and DRAM block 0 and 1 address and control registers (configured in DACR0
and DACR1). If the driven address compares with one of the programmed chip selects or DRAM
blocks, the appropriate chip select is asserted or the DRAM block is selected using the
specifications programmed by the user in the respective configuration register. Otherwise, the
following occurs:
17-4
• If the address and attributes do not match in CSCR or DACR, the MCF5271 runs an
external burst-inhibited bus cycle with a default of external termination on a 32-bit port.
shows the byte lanes that external memory should be connected to and the sequential
Figure 17-2. Connections for External Memory Port Sizes
Figure 17-3. Chip-Select Module Output Timing Diagram
CLKOUT
CS[7:0]
BS[3:0]
OE
Byte Enable
32-Bit Port
16-Bit Port
Processor
Data Bus
8-Bit Port
External
Memory
Memory
Memory
MCF5271 Reference Manual, Rev. 2
D[31:24]
Byte 0
Byte 0
Byte 2
Byte 0
Byte 1
Byte 2
Byte 3
BS3
D[23:16]
Byte 1
Byte 1
Byte 3
BS2
indeterminate values
Driven with
indeterminate values
D[15:8]
Byte 2
BS1
Driven with
Byte 3
D[7:0]
BS0
Freescale Semiconductor