MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 277

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

14.4
In the following discussion, the term ‘DMA request’ implies that DCRn[START] or
DCRn[EEXT] is set, followed by assertion of and internal or external DMA request. The START
bit is cleared when the channel begins an internal access.
Before initiating a dual-address access, the DMA module verifies that DCRn[SSIZE,DSIZE] are
consistent with the source and destination addresses. If they are not consistent, the configuration
error bit, DSRn[CE], is set. If misalignment is detected, no transfer occurs, DSRn[CE] is set, and,
depending on the DCR configuration, an interrupt event is issued. Note that if the auto-align bit,
DCRn[AA], is set, error checking is performed on the appropriate registers.
Freescale Semiconductor
Bits
5–4
3-2
1-0
Functional Description
LINKCC
Name
LCH1
LCH2
Table 14-4. DCRn Field Descriptions (Continued)
Link channel control. Allows DMA channels to have their transfers linked. The current
DMA channel will trigger a DMA request to the linked channels (LCH1 or LCH2) depending
on the condition described by the LINKCC bits.
00 No channel-to-channel linking
01 Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to
10 Perform a link to channel LCH1 after each cycle-steal transfer
11 Perform a link to channel LCH1 after the BCR decrements to zero
If not in cycle steal mode (DCRn[CS]=0) and LINKCC=01 or 10, then no link to LCH1 will
occur.
If LINKCC = 01, a link to LCH1 is created after each cycle-steal transfer performed by the
current DMA channel is completed. As the last cycle-steal is performed and the BCR
reaches zero, then the link to LCH1 is closed and a link to LCH2 is created.
If the LINKCC field is non-zero, the contents of the bandwidth control field (DCRn[BWC])
are ignored and effectively forced to zero by the DMA hardware. This is done to prevent
any non-zero bandwidth control settings from allowing channel arbitration while any type
of link is to be performed.
Link channel 1. Indicates the DMA channel assigned as link channel 1. The link channel
number cannot be the same as the currently executing channel, and generates a
configuration error if this is attempted (DSRn[CE] is set).
00 DMA Channel 0
01 DMA Channel 1
10 DMA Channel 2
11 DMA Channel 3
Link channel 2. Indicates the DMA channel assigned as link channel 2. The link channel
number cannot be the same as the currently executing channel, and generates a
configuration error if this is attempted (DSRn[CE] is set).
00 DMA Channel 0
01 DMA Channel 1
10 DMA Channel 2
11 DMA Channel 3
LCH2 after the BCR decrements to zero.
MCF5271 Reference Manual, Rev. 2
Description
Functional Description
14-13