MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 478

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

I
25.4.2 Slave Address Transmission
The master sends the slave address in the first byte after the START signal (B). After the seven-bit
calling address, it sends the R/W bit (C), which tells the slave data transfer direction (0 = write
transfer, 1 = read transfer).
Each slave must have a unique address. An I
cannot be master and slave at the same time.
The slave whose address matches that sent by the master pulls I2C_SDA low at the ninth serial
clock (D) to return an acknowledge bit.
25.4.3 Data Transfer
When successful slave addressing is achieved, the data transfer can proceed (E) on a byte-by-byte
basis in the direction specified by the R/W bit sent by the calling master.
Data can be changed only while I2C_SCL is low and must be held stable while I2C_SCL is high,
as
receiving device must acknowledge each byte by pulling I2C_SDA low at the ninth clock;
therefore, a data byte transfer takes nine clock pulses. See
25.4.4 Acknowlege
The transmitter releases the I2C_SDA line high during the acknowledge clock pulse as shown in
Figure
that it remains stable low during the high period of the clock pulse.
If it does not acknowledge the master, the slave receiver must leave I2C_SDA high. The master
can then generate a STOP signal to abort the data transfer or generate a START signal (repeated
start, shown in
calling sequence.
25-4
2
C Interface
Figure 25-2
I2C_SDA
I2C_SCL
25-4. The receiver pulls down the I2C_SDA line during the acknowledge clock pulse so
START
Signal
Bit7
shows. I2C_SCL is pulsed once for each data bit, with the msb being sent first. The
1
Figure 25-5
Bit6
2
Slave Address
Bit5
3
Bit4 Bit3 Bit2 Bit1
4
and discussed in
5
MCF5271 Reference Manual, Rev. 2
Figure 25-3. Data Transfer
6
7
I2C_SCL Held Low while
Bit0
R/W
Interrupt is Serviced
8
ACK from
Receiver
2
C master must not transmit its own slave address; it
Section 25.4.6, “Repeated
9
Bit7
(Byte Complete)
Interrupt Bit Set
1
Bit6
2
Figure
Bit5
3
Data Byte
Bit4 Bit3 Bit2 Bit1
25-3.
4
5
START”) to start a new
6
Freescale Semiconductor
7
Bit0
8
ACK
No
Bit
9
Signal
STOP