MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 350

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Fast Ethernet Controller (FEC)
19.2.2 Register Memory Map
Table 19-2
description.
19.2.3 MIB Block Counters Memory Map
Table 19-3
space where hardware maintained counters reside. These fall in the 0x1200-0x13FF address offset
range. The counters are divided into two groups.
19-6
IPSBAR Offset
defines the MIB Counters memory map which defines the locations in the MIB RAM
shows the FEC register memory map with each register address, name, and a brief
0x10EC
0x10C4
0x10E4
0x10E8
0x114C
0x1004
0x1008
0x1010
0x1014
0x1024
0x1040
0x1044
0x1064
0x1084
0x111C
0x1118
0x1120
0x1124
0x1144
0x1150
0x1180
0x1184
0x1188
Table 19-2. FEC Register Memory Map
EMRBR
ERDSR
MDATA
ETDSR
MSCR
GAUR
TFWR
RDAR
Name
TDAR
PAUR
GALR
FRBR
FRSR
EIMR
MIBC
PALR
IAUR
ECR
RCR
OPD
IALR
TCR
EIR
MCF5271 Reference Manual, Rev. 2
Upper 32 bits of Individual Hash Table
Lower 32 Bits of Individual Hash Table
Transmit Descriptor Active Register
FIFO Receive FIFO Start Registers
Pointer to Transmit Descriptor Ring
Receive Descriptor Active Register
Physical Address High+ Type Field
Upper 32 bits of Group Hash Table
Lower 32 bits of Group Hash Table
Pointer to Receive Descriptor Ring
Physical Address Low Register
FIFO Receive Bound Register
Maximum Receive Buffer Size
MIB Control/Status Register
MII Speed Control Register
Opcode + Pause Duration
Transmit FIFO Watermark
Transmit Control Register
Ethernet Control Register
Receive Control Register
Interrupt Event Register
Interrupt Mask Register
MII Data Register
Description
Freescale Semiconductor
(bits)
Size
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32